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DS90UB954-Q1: When 0x7c register is configured 0xc0, split screen will appear, otherwise, black screen will appear

Part Number: DS90UB954-Q1

When 0x7c register is configured 0xc0, split screen will appear, otherwise, black screen will appear

maybe bit[5] DISCARD_ON_PAR_ERR worked. However, the serializer is ti953 be configed ais csi mode. 0x7c worked on raw mode.

so in my opinion no matter whether 0x7c is configured or not, it will not affect the output on csi mode,is right?

Now on raw mode ,it affect output, can u give a hand ?

  • Hello,

    Your assumption is correct, if you are using the 953 as the serializer then it should be operating in CSI mode and changing the 10-bit settings won't have any affect.  If there are errors occurring then that may cause issues like the ones seen above.  I would suggest looking at registers 0x4D and 0x4E to see if any errors are occurring on that port.  If errors are occurring then it may be necessary to verify that the channel meets the recommendations in the datasheet.  

    Regards,

    Nick

  • Hi Nick

    1. in fact  ,if set the  0x7c (serializer  953 csi mode.),high probability occurrence split .

    if do not set 0x7c,low probability occurrence split .but maybe have dark screen. means no output.

    2. when split  read the value as follows

    [0xdB  0x4d 0x4e]   data is  [0x7b, 0x33, 0xfd]

    and 0x7A = 0xf

    some advice?

    thanks

  • Hello,

    The registers that were pulled I am assuming that they match respectively like below:

    0xDB: 0x7B,

    0x4D: 0x33,

    0x4E: 0xFD

    But this shows that there are some errors in the link.  It may be worthwhile to run the MAP tool in Analog Launch PAD which is described here https://www.ti.com/lit/ug/snlu243/snlu243.pdf?ts=1591288007527.  

    Also what are the settings you are using for the internally generated framesync?

    Regards,

    Nick

  • Hi Nick

    from the link ,we will check the AEQ.

     the internally generated framesync do u mean register 0x18(FS_CTL)? 

    do not set 0x18 ,use its default value.

    How to configure it?

    Thanks

  • By the way ,u are right, the data as below: 

    0xDB: 0x7B,

    0x4D: 0x33,

    0x4E: 0xFD

    0x7A : 0x0F

  • Okay sorry for the confusion, I saw the original question linked was regarding the internal frame sync generator.  If it is not being used then no need to configure it here.

    Regards,

    Nick

  • Hi Nick

    ok,let us focus on the settings.

    I test the setting again.

    if set the  0x7c [c0] (serializer  953 csi mode.), first open , it must be split.

    if do not set 0x7c,first open,it do not have split.

    why?

     from  datasheet  can see on csi mode ,no matter whether 0x7 is set or not, it should not work.(means set or not ,do not affect the output)

    in fact ,it affect the output on csi mode. why?

    by the way ,if do not set 0x7c,low probability occurrence dark screen( means no output.)

    thanks

  • Hello again,

    I think I am confused here.  If you are not operating in 10-bit mode (operating in CSI-mode) then there is no reason to set those bits.  I am not sure of the effects setting these bits would have on CSI mode, I would think there would be no effect.  If you are operating in CSI mode with a 953 as the serializer then I would not set 0x7c.  Also are there any conclusions to be draw from the testing the link?

    Regards,

    Nick

  • Hi Nick

    ok, in fact,we do not config 0x7c in csi mode(953),  

    test the AEQ is ok,meet the requirements.

    However, there also will be occasional split . how to check it ?

    is  954 have  any way to detect an error and discard it ?  in csi mode ,0x6d bit[6] bit[5] bit[4] bit[3] set  0  is right ?

    if it is , in raw mode which register to config?

    thanks

  • HI Nick

     0x4D bit[0]  is 1 , do it  means the 954 receive the input data have no errors?

  • Hello,

    No, so there can be lock with some errors, the term lock simply means that the device is able to lock onto the clock of the FPD-Link signal.  There may still be errors in the transmission and will typically set other error bits in register ox4D and 0x4E.

    Regards,

    Nick