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Original question:

DS125DF1610: DS125DF1610: CDR lock problems using DS125DF1610 crosspoint and broadcast function

DS125DF1610: CDR lock problems using DS125DF1610 crosspoint and broadcast function, follow-up

Romain Ducaffy
Prodigy 160 points
Part Number: DS125DF1610

Hello,

This is a follow-up to this thread which has been locked when I could not access the setup to to confinement measures where I live.

I tested again the setup and, again, forcing signal detect to HIGH on channel A causes channel B TX to lock. However, when I deassert signal detect HIGH on channel A, channel B TX unlocks immediately.

I also tried this: Starting from my initial workaround (routing of channel B RX to channel C TX), where channel B TX is locked, I force signal detect high on all four channels of the quad. Then, I change the crosspoint to the initially intended configuration (A RX fans out to A, C and D TX, C RX routed to B TX ; channel B TX is still locked). Finally, I deassert signal detect high on all four channels of the quad. At this time, channel B TX is unlocked.

So the workaround (asserting signal detect high while changing crosspoint configuration, then deassert signal detect high) does not work in my case. Leaving signal detect high could be a workaround, but then I lose the actual information of the signal detect status.

Any advice would be appreciated.

Regards,
--
RD

  • 0
    TI__Mastermind 19235 points

    Hi,

    • Can you remind me what specific DS125DF1610 crosspoint configuration are you using for your test?
      • Fanout a channel to multiple outputs within quad?
      • channels crossing within quad?
      • Muxing multiple channels within quad to a single output?

    • What are your current values being implemented for the following channel registers?
      • 0x31
      • 0x2F
      • 0x14
      • 0x95
      • 0x96
      • 0x9B

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • 0 in reply to Rodrigo Natal
    Prodigy 160 points

    Hello,

    My setup is exactly the same as in the related thread, as I have mentioned, since this is a follow-up to a locked thread.

    Register values :
    For the test case where channel B is unlocked (first scenario):
    Channel B
      0x14 = 0x00
      0x2F = 0xB6
      0x31 = 0x00
      0x95 = 0x00
      0x96 = 0x1E
      0x9B = 0x02
    Channel C
      0x14 = 0x00
      0x2F = 0xB6
      0x31 = 0x00
      0x95 = 0x00
      0x96 = 0x1C
      0x9B = 0x00


    For the test case where channel B is locked after changing the crosspoint configuration (channel B RX to channel C TX, second scenario):
    Channel B
      0x14 = 0x00
      0x2F = 0xB6
      0x31 = 0x00
      0x95 = 0x00
      0x96 = 0x1E
      0x9B = 0x02
    Channel C
      0x14 = 0x00
      0x2F = 0xB6
      0x31 = 0x00
      0x95 = 0x00
      0x96 = 0x1D
      0x9B = 0x01


    Return to first scenario, force signal detect high:
    Channel B
      0x14 = 0x80
      0x2F = 0xB6
      0x31 = 0x00
      0x95 = 0x00
      0x96 = 0x1E
      0x9B = 0x02
    Channel C
      0x14 = 0x80
      0x2F = 0xB6
      0x31 = 0x00
      0x95 = 0x00
      0x96 = 0x1C
      0x9B = 0x00

    Then deassert signal detect high:
    Channel B
      0x14 = 0x00
      0x2F = 0xB6
      0x31 = 0x00
      0x95 = 0x00
      0x96 = 0x1E
      0x9B = 0x02
    Channel C
      0x14 = 0x00
      0x2F = 0xB6
      0x31 = 0x00
      0x95 = 0x00
      0x96 = 0x1C
      0x9B = 0x00

    Regards,

    --

    RD

  • 0 in reply to Romain Ducaffy
    TI__Mastermind 19235 points

    Hi,

    Can you confirm what input signal data rate and pattern you are using for each of the retimer channels under test? Based on your setting of 0x2F I would assume 10.3125Gbps data rate but would like to confirm.

     If you simultaneously apply a valid input signal to each of the four channels in the quad (A thru D) while setting each channel to normal pass through mode, are you able to see signal detect assert and data output on all channels with 0x14[7]=0?

    Your crosspoint register settings (i.e. for 96 and 9B) for each of the channels appear to be correct.

    Regards,

    Rodrigo Natal

    HSSC Applications Engineer

     

  • 0 in reply to Rodrigo Natal
    Prodigy 160 points

    Hello,

    "Can you confirm what input signal data rate and pattern you are using for each of the retimer channels under test? Based on your setting of 0x2F I would assume 10.3125Gbps data rate but would like to confirm."
    -> Yes, 10.3125Gbps indeed. I am not using a custom pattern, mostly actual data from SERDES FPGA IPs. At the very least the syncword, when there is no actual data.

    " If you simultaneously apply a valid input signal to each of the four channels in the quad (A thru D) while setting each channel to normal pass through mode, are you able to see signal detect assert and data output on all channels with 0x14[7]=0?"
    -> Yes. Even with a crosspoint configuration enabled, as long as a valid input signal is actually fed to all inputs, all channels detect signal, lock and transmit signal without an issue.

    Regards,
    --
    RD

  • 0 in reply to Romain Ducaffy
    TI__Mastermind 19235 points

    Hi RD,

    Thanks for the info. At this point I'm not able to find an explanation for behavior you are observing. The best recommendation I can offer is to keep signal detect force asserted on all the channels during operation, which as you noted takes away the retimer signal detect status as a diagnostic function.

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer