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Original question:

DS125DF1610: CDR lock problems using DS125DF1610 crosspoint function

DS125DF1610: DS125DF1610: CDR lock problems using DS125DF1610 crosspoint and broadcast function

Romain Ducaffy
Prodigy 160 points

Part Number: DS125DF1610

Hello,

This issue relates to what I called "third issue" in https://e2e.ti.com/support/interface/f/138/t/823638.

The hardware setup is identical. Here I am in a situation where, in quad 0 of the retimer, I want to route signal from C RX to B TX, the other channels being unused. Here is my crosspoint configuration:


config nok

The unused outputs configuration is left to default, meaning all are routed from channel A RX. Crosspoint, local and multi-drive buffer are on on all channels. All channels are allowed to lock (shared registers 0x0F and 0x10 are set to 0xFF) and concurrent lock limit is set to 15 (register 0x05 is set to 0x1F).

In this configuration, channel B TX CDR is unlocked. Signal detect status is up though.

If I change the routing of channel C TX to channel B RX (no signal incoming), then channel B TX locks.


The configuration works here, but I do not understand why. I need to know what is happening because this is just one example of the configurations I would like to use. The configuration may change dynamically and I need to know what is supposed to work or not in order to configure the retimer properly.

Have a nice day. Regards,

--
RD

  • 0
    TI__Mastermind 19235 points

    Hi,

    I could use some additional info to assist my troubleshooting:

    1. For the test case where channel B is unlocked what are the values for the following channel registers for both channels B and C?
      • 0x02, 0x96, and 0x9B
    2. For the test case where channel B is locked what are the values for the following channel registers for both channels B and C?
    • 0x02, 0x96, and 0x9B
    • 0x8F
    • 0x27 and 0x28

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • 0 in reply to Rodrigo Natal
    Prodigy 160 points

    Hello Rodrigo,

    For the test case where channel B is unlocked
    Channel B
      0x02 = 0x00
      0x96 = 0x1E
      0x9B = 0x02
    Channel C
      0x02 = 0x04
      0x96 = 0x1C
      0x9B = 0x00

    For the test case where channel B is locked
    Channel B
      0x02 = 0xDC
      0x96 = 0x1E
      0x9B = 0x02
      0x8F = 0x00
      0x27 = 0x36
      0x28 = 0x72
    Channel C
      0x02 = 0x00
      0x96 = 0x1D
      0x9B = 0x01
      0x8F = 0x00
      0x27 = 0x00
      0x28 = 0x00

    Note that I am disabling CLTE adaptation (reg 0x2D[3]=0b1) and forcing eq boost to 0/0/0/0 (reg 0x03=0x00). Also note that in the second situation, channel C TX is unlocked, as expected, hence the eye opening measurement to zero.

    Regards,
    --
    RD

  • 0 in reply to Romain Ducaffy
    TI__Mastermind 19235 points

    Thanks for the info. The issue is that you have configured the crosspoint channels incorrectly on the case where channel B CDR is not locked. The correct values are:

    • Channel B: 0x96 = 0x1E, 0x9B = 0x02
    • Channel C: 0x96 = 0x1D, 0x9B = 0x01

    Regards,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    TI__Mastermind 19235 points

    Hi,

    I misinterpreted your crosspoint settings. For the case where A is fanned out to A C and D and B outputs C the following settings apply.

    • Channel A: 0x96=0x04, 0x9B=0x00
    • Channel B: 0x96=0x1E, 0x9B=0x02
    •  Channel C:  0x96=0x1C, 0x9B=0x00
    • Channel D: 0x96=0x1C, 0x9B=0x00

    regards,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Prodigy 160 points

    Hello,

    I tried this but this did not solve the problem: channel B is still unlocked. For information, here are the values of the same registers as last time:


    Channel A
      0x02 = 0x00
      0x96 = 0x04
      0x9B = 0x00
    Channel B
      0x02 = 0x00
      0x96 = 0x1E
      0x9B = 0x02
    Channel C
      0x02 = 0x00
      0x96 = 0x1C
      0x9B = 0x00

    Regards,
    --
    RD

  • 0 in reply to Romain Ducaffy
    TI__Mastermind 19235 points

    Hi,

    If you force signal detect asserted by setting channel register 0x14[7]=1 on all four channels in the crospoint quad does your result change?

    Table 14. Channel Registers, 0 to 1F (continued)

    Address

    (Hex)

    Bits

    Default Value (Hex)

    Mode

    EEPROM

    Field Name

    Description

    14

    7

    0

    RW

    Y

    EQ_SD_PRESET

    1: Forces signal detect HIGH, and force enables the channel. Should not be set if bit 6 is set.

    0: Normal Operation.

    6

    0

    RW

    Y

    EQ_SD_RESET

    1: Forces signal detect LOW and force disables the channel. Should not be set if bit 7 is set.

    0: Normal Operation.

    5

    0

    RW

    Y

    EQ_REFA_SEL1

    Controls the signal detect assert levels.

    4

    0

    RW

    Y

    EQ_REFA_SEL0

    3

    0

    RW

    Y

    EQ_REFD_SEL1

    Controls the signal detect de- assert levels.

    2

    0

    RW

    Y

    EQ_REFD_SEL0

    1:0

    0

    RW

    N

    RESERVED

  • 0 in reply to Rodrigo Natal
    Prodigy 160 points

    Hello,

    Yes, it does. I went a little further and noticed forcing signal detect on channel A was enough to cause channel B TX to lock. I do not understand why though.

    Regards,
    --
    RD

  • 0 in reply to Romain Ducaffy
    TI__Mastermind 19235 points

    Hi Romain,

    During retimer evaluation we had identified an issue with signal detect block calibration for some crosspoint configuration cases. The issue can be worked around by forcing signal detect high on the crosspoint channels when the crosspoint configuration is being changed; the signal detect HIGH condition can be subsequently removed after the crosspoint configuration is finalized.

    Regards,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Prodigy 160 points

    Hello Rodrigo,

    Thank you for your input.

    I will try this more extensively. Unfortunately, due to containment measures in place where I live, I have not been able to have access on that setup for a few days. I will let you know here when I have more information on this.

    Regards,
    --
    RD