SN65DPHY440SS: SN65DPHY440SS

Does anybody know how to debug int further, a known working configuration or what I have done wrong because I have check my Zdiffs and stuff and it seems to be fine.

Hi,

Can I take a look at your schematic? Can you also probe the DPHY440 input and output? Are you seeing the correct transition between the LP and HS mode?

Thanks

David

Hi David,

Yes, sure, you can find it attached below. I do see signals coming out of the cameras, through the SN65 and into the Jetson. I do not have a differential probe but they do resemble the signal coming out of the working camera for what it's worth...

MIPI.pdf

Shoot, my variant wasn't exported properly.
The only mounted setting resistors are R139 and R180.

Hi,

Looking at the schematic, I noticed one thing.

For all CSI-2 implementations, the polarity must be maintained between the CSI-2 Source and CSI-2 Sink. The DPHY440 does not support polarity inversion. It looks like you have the polarity swapped between the input and the output.

Also, lane 0 is the only bi-directional lane, I would use lane 1, lane 2, and the clock lane, and have lane 0 and 3 connected to GND.

Thanks

David

Dear David, boy, how did I not notice that? Thank you! 

I will try patching the swapped pins, do you think (if the patching is going to work) the board will be usable with lane 0? 

Hi,

The DPHY440’s LP TX is expecting to connect to an unterminated LP RX.  With Lane 0 path (DA0P/N and DB0P/N) supporting bi-directional LP signaling, it is very important that DB0P/N LP TX is connected to an unterminated LP RX.  If DB0P/N LP TX is connected to a HS RX, then LP signaling will not be able to reach the LP11 levels and which will cause the DPHY440 to not enable HS data path on Lane0.

If you ran into an issue with lane 0, there is a workaround to enable HS path for Lane 0 only:

Write Register 0x50 with 8’h01 //Override enable for HS TX path

Write Register 0x51 with 8’h01 //HS TX path enabled.

Write Register 0x61 with 8’h00  // Disable LP path.

Write Register 0x70 with 8’h01  //Override enable for HS RX path

Write Register 0x71 with 8’h01  // HS RX path enabled.

Bit 0 is lane 0

Thanks

David

Dear David,

Thank you for your help! I did not manage to get the polarity inversion swapped. Do you perhaps know if there is any way at all to get this fixed still? Perhaps a similar IC which supports inversion?

These are the swapped traces: 

Dear David,

Would the very low-tech solution of swapping the input pins into the IC work, perhaps? Putting the P on the N pin on the input as well?

Regards,

Alexander

Alexander

You could cut the traces, and then use the magnet wire to swap the polarity. The signal integrity will be degraded depending on the data rate.

Thanks

David

Dear David

I assume the wires would have to be as short as possible to make this work? I have tried going from the vias you see on the picture to the SODIMM but got nothing.
I will play around with it some more, thank you!

Regards

Alexander