DS90UB936-Q1: Pattern generation issue with UB936

Hello Trishala,

Your register setup looks fine. If you are having trouble, verify that you are following these instructions outlined in the pattern generation section of the datasheet:

1. Disable video forwarding by setting bits [5:4] of the FWD_CTL1 register (that is, set register 0x20 to 0x30).

2. Configure CSI-2 Transmitter operating speed using the CSI_PLL_CTL register.

3. Enable the CSI-2 Transmitter for port 0 using the CSI_CTL register

Thank you,

Carrie

Hi Carrie

1.WriteI2C(0x20,0x30)

2. WriteI2C(0x02,0x1F)

3.WriteI2C(0x33,0x01)

Can you tell me the settle count value.. I am working with the QNX there we have to SETTLE_COUNT.. Will it be the same as that of the REFCLK or is there any thing else

Hello Trishala,

What value did you set in the CSI_PLL_CTL register (Address 0x1F)? Also, what CSI rate is the SoC programmed to receive? I am working on the answer to your question about settle_count and will get back to you tomorrow.

Regards,

Carrie

Hi Carrie

Sorry for my mistake I have set 0x02 value to CSI_PLL_CTL register (Address 0x1F).

Also, what CSI rate is the SoC programmed to receive?

------------------------------------------------------------------------

Ans:200MHz

------------------------------------------------------------------------

Thanks

Trishala

Hello Trishala,

The 936 CSI-2 timing parameters, including settle values, are qualified with the MIPI specification. The register defaults for the timing parameters comply with the standards and should not be altered, unless a data rate of 400 Mbps is used, in which case they should be written according to datasheet section 7.4.21.

With your SoC expecting a clock frequency of 200MHz, the 936 should be transmitting data at the same rate, which is 400 Mbps. This requires changing CSI_PLL_CTL bits 1:0 to 0b11 and adjusting the timing parameters to meet MIPI standards as mentioned above (section 7.4.21).

If this doesn’t fix your problem, verify other CSI-2 controls on the 936 such as skew calibration and continuous clocking.

Regards,

Carrie

Hi Carrie

The section 7.4.21 has to be done before configuring the register 0x1f to 0b11 ?

Can you tell us the flow of register configuration

Thanks

Trishala

HI Carrie

Another thing I have tried other CSI-2 controls on the 936 such as skew calibration and continuous clocking. but it is still not working.. No CSI packets are generated.. Can you also tell the initialisation of deserliazer and do we need to configure FPD3_PORT_SEL register before the pattern generation .

Thanks

Trishala

Hello Trishala,

As long as all relevant registers are set before the start of the transmission, it should work fine.

Can you please send me a complete register dump for the 936 just prior to enabling the pattern generator? I can take a look at it and also comment on whether or not the order of any of the configuration matters

Thanks,

Carrie

Hi Carrie

The only configuration I have done is for the register address 0x4C. The value set is 0x03. After that I have set for pattern generation

Address 0x20--> value= 0x30,
Address -->0xB0-->value=0x02
Address -->0xB1-->value=0x40
Address --> 0xB2-->value=0x83
Address -->0xB2-->value=0x8D
Address -->0xB2-->value=0x87
Address -->0xB2-->value= 0x87
Address -->0xB2-->value=0x83
Address -->0xB2-->value= 0x86,
Address --> 0xB2-->value= 0x84

Address -->0xB2-->value= 0x86
Address --> 0xB2-->value= 0x84
Address -->0x1F-->value=0x03
 Address -->0x33, 0x43
Address --> 0xB0, 0x00
 Address -->0xB1, 0x01
 Address -->0xB2, 0x01
 Address -->0xB1, 0x02
 Address --> 0xB2, 0x33
 Address -->0xB1, 0x03
Address --> 0xB2, 0x24
Address -->0xB1, 0x04
Address --> 0xB2, 0x0F
Address --> 0xB1, 0x05

Address --> 0xB2-->value=0x00
Address -->0xB1-->value= 0x06
Address -->0xB2-->value= 0x01
 Address --> 0xB1-->value= 0x07
Address --> 0xB2-->value=0xE0
Address --> 0xB1-->value=0x08
Address --> 0xB2-->value=0x02
Address --> 0xB1-->value= 0x09
Address --> 0xB2-->value= 0xD0
Address -->0xB1-->value= 0x0A
Address -->0xB2-->value= 0x04
Address --> 0xB1-->value= 0x0B
Address --> 0xB2-->value=0x1A
Address --> 0xB1-->value= 0x0C
 Address --> 0xB2-->value= 0x0C
Address -->0xB1-->value= 0x0D
 Address --> 0xB2-->value=0x67
Address -->0xB1-->value=0x0E
Address --> 0xB2-->value= 0x21
Address --> 0xB1-->value= 0x0F
Address --> 0xB2-->value= 0x0A

Hello Trishala,

I am replicating your setup in the lab and will get back to you by Thursday. If your configuration works on my end, it is probably an SoC problem. If it doesn’t, then I will get it working and send you the working script.

Regards,

Carrie

Hello Trishala,

I wrote a script emulating your register writes (see attached) and ran it with my replicated setup in the scripting tab of Analog LaunchPAD. I was able to successfully generate an image, verified with a CSI-Analyzer.

This leads me to suspect that your issue is an SoC error or possibly a schematic error. If you have the EVM, I would recommend running the attached script. If not, send me more details about the issues you are encountering or your setup and I will see if I can find the source of the error.

Regards,

Carrie

'''
Ran as PreDefScript in scripting tab of AnalogLaunchPAD
'''

board.WriteReg(0x20, 0x30) # Disable video forwarding of FWD_CTL1 Register

# Adjusting for 400 Mbps
board.WriteReg(0xB0, 0x02) # Set Auto-increment, page 0
board.WriteReg(0xB1, 0x40) # CSI Port 0
board.WriteReg(0xB2, 0x83) # TCK Prep
board.WriteReg(0xB2, 0x8D) # TCK Zero
board.WriteReg(0xB2, 0x87) # TCK Trail
board.WriteReg(0xB2, 0x87) # TCK Post
board.WriteReg(0xB2, 0x83) # THS Prep
board.WriteReg(0xB2, 0x86) # THS Zero
board.WriteReg(0xB2, 0x84) # THS Trail
board.WriteReg(0xB2, 0x86) # THS Exit
board.WriteReg(0xB2, 0x84) # TLPX

board.WriteReg(0x1F, 0x03) # Set CSI tx speed to 400 Mbps
board.WriteReg(0x33, 0x43) # Set CSI lane count to 4, cont. clock, enable 

# Indirect Access Register Programming
board.WriteReg(0xB0, 0x00) # Set page 0
board.WriteReg(0xB1, 0x01)
board.WriteReg(0xB2, 0x01)
board.WriteReg(0xB1, 0x02)
board.WriteReg(0xB2, 0x33)
board.WriteReg(0xB1, 0x03)
board.WriteReg(0xB2, 0x24)
board.WriteReg(0xB1, 0x04)
board.WriteReg(0xB2, 0x0F)
board.WriteReg(0xB1, 0x05)
board.WriteReg(0xB2, 0x00)
board.WriteReg(0xB1, 0x06)
board.WriteReg(0xB2, 0x01)
board.WriteReg(0xB1, 0x07)
board.WriteReg(0xB2, 0xE0)
board.WriteReg(0xB1, 0x08)
board.WriteReg(0xB2, 0x02)
board.WriteReg(0xB1, 0x09)
board.WriteReg(0xB2, 0xD0)
board.WriteReg(0xB1, 0x0A)
board.WriteReg(0xB2, 0x04)
board.WriteReg(0xB1, 0x0B)
board.WriteReg(0xB2, 0x1A)
board.WriteReg(0xB1, 0x0C)
board.WriteReg(0xB2, 0x0C)
board.WriteReg(0xB1, 0x0D)
board.WriteReg(0xB2, 0x67)
board.WriteReg(0xB1, 0x0E)
board.WriteReg(0xB2, 0x21)
board.WriteReg(0xB1, 0x0F)
board.WriteReg(0xB2, 0x0A)

HI Carrie

I just wanted to know that if there is any other HW Errata workaround needed to initialise the deserializer which I might be missing i.e if you have only used this registers which you have mentioned in script?

I don't have the 936 library files and I am using 960 library files. I hope it wouldn't matter with that . I am using qualcomm SOc

Thanks

Trishala

Hello Trishala,

I have only configured the registers that I provided in the script. There is an error in the configuration that I detected after your last message, which is that the line period needs to be adjusted to account for the change in units from 10ns to 20ns (caused by tx rate of 400 Mbps). The line_pd1 and 0 registers should be changed from 0x0C67 to 0x0633.

You can try resetting the Deserializer between attempts. This will reset the registers to their defaults, which was the configuration I ran the script with to get the pattern generator working.

The library differences shouldn’t be an issue in this case.

Do you have any confirmation that you are able to successfully access the registers with the Qualcomm SoC? Make sure that you have the right I2C address (7 bit default is 0x3D) and that you are using the correct configuration (7 bit or 8 bit I2C addressing).

Additionally, please send over your schematic so I can check the CSI interface and make sure there aren’t any issues with that configuration.

Regards,

Carrie

Hi Carrrie

I am able to successfully access the registers with the Qualcomm soc as I have checked the values of the registers they are being configured properly.

Make sure that you have the right I2C address------ yes the address for us is 0x68 .. I have confirmed it .. The configuration is done with 8 bit i2c addressing configuration.

I will try sending you the schematic...

In the meantime i checked on with my device _status_register (0x04)-- it showed me the value as 0xd3---I guess this is ok..

And for the pattern generation what should be lock and pass status .. will the lock and pass pin status needed required for this ? if yes the register address 0x7D(PORT_PASS_CTL) shows the value 0xB9

if the lock and pass ctl is needed what is needed to be configured

Thanks

Trishala

Hi Carrrie

NEW_PWB24915_19_Nov_2019_new-pages-10.pdf

The EN_1V1 and the PDB is connected to the SOC. And to power up the TI deserializer first EN_1V1 has to put from low pulse to high pulse and after a delay of 5ms PDB is made from low to high. Please let me know if you find anything.. and if at all it is possible to have a meeting scheduled if you don't find any discrepancy in the schematics. so that we can come to an conclusion as soon as possible

Thanks

Trishala

Hi Trishala,

Your schematic seems fine. It is recommended to add separate .01uF capacitors to each VDD_FPD pin, instead of having pins 34 and 43 share one, and pins 36 and 45 share one

Have you tried PatGen from the serializer? If so, are you seeing the same issue?

Can you please send me exactly what errors the SoC is reporting, if any?

Thank you,

Carrie

Hi Carrie

do the lock and pass pin status matter for this. And no errors has been reported from the soc side . in the meanwhile i will try from the serializer end

Thanks

trishala

Hi Carrie

I need two things from you one is i need you to send me how to calculate the line_pd1 and 0 and another thing which I need is that I need want the pattern generation for YUV422 format with 8bit can you send me the register configuration for this. Plus if you could answer my pass and lock pin status response..

"n the meantime i checked on with my device _status_register (0x04)-- it showed me the value as 0xd3---I guess this is ok..

And for the pattern generation what should be lock and pass status .. will the lock and pass pin status needed required for this ? if yes the register address 0x7D(PORT_PASS_CTL) shows the value 0xB9"

This is what I have send you earlier didn't get a response for this

Thanks

Trishala

Hello Trishala,

Line period is calculated using frame rate and lines per frame.  Line_pd = 1/(frame_rate * total_lpf). To convert to 10 ns units, multiply that value by 10^8. For a 400 Mbps data rate, the unit size of the line period register becomes 20 ns (see section 7.5.11.2 of the datasheet). This means that the line period needs to be scaled by (10 ns / 20 ns) or 1/2 .

For YUV422 8 bit format, set the PGEN_CSI_DT register 0x03 to 0x1E. The first 6 bits control the data type and the last 2 can be changed to reflect the desired VC-ID. I am attaching the working PatGen script that I sent earlier, modified for 1280x720p with YUV422 8 bit format.

As far as Pass status, this is for verifying successful link to the serializer and is not relevant when considering the deserializer pattern generation. I am looking into Lock and will get back to you.

'''
Ran as PreDefScript in scripting tab of AnalogLaunchPAD
'''

board.WriteReg(0x20, 0x30) # Disable video forwarding of FWD_CTL1 Register

# Adjusting for 400 Mbps
board.WriteReg(0xB0, 0x02) # Set Auto-increment, page 0
board.WriteReg(0xB1, 0x40) # CSI Port 0
board.WriteReg(0xB2, 0x83) # TCK Prep
board.WriteReg(0xB2, 0x8D) # TCK Zero
board.WriteReg(0xB2, 0x87) # TCK Trail
board.WriteReg(0xB2, 0x87) # TCK Post
board.WriteReg(0xB2, 0x83) # THS Prep
board.WriteReg(0xB2, 0x86) # THS Zero
board.WriteReg(0xB2, 0x84) # THS Trail
board.WriteReg(0xB2, 0x86) # THS Exit
board.WriteReg(0xB2, 0x84) # TLPX

board.WriteReg(0x1F, 0x03) # Set CSI tx speed to 400 Mbps
board.WriteReg(0x33, 0x43) # Set CSI lane count to 4, cont. clock, enable 

# Indirect Access Register Programming
board.WriteReg(0xB0, 0x00) # Set page 0
board.WriteReg(0xB1, 0x01)
board.WriteReg(0xB2, 0x01)
board.WriteReg(0xB1, 0x02)
board.WriteReg(0xB2, 0x34)
board.WriteReg(0xB1, 0x03)
board.WriteReg(0xB2, 0x1E) #YUV422 8 bit
board.WriteReg(0xB1, 0x04)
board.WriteReg(0xB2, 0x0A)
board.WriteReg(0xB1, 0x05)
board.WriteReg(0xB2, 0x00)
board.WriteReg(0xB1, 0x06)
board.WriteReg(0xB2, 0x01)
board.WriteReg(0xB1, 0x07)
board.WriteReg(0xB2, 0x40)
board.WriteReg(0xB1, 0x08)
board.WriteReg(0xB2, 0x02)
board.WriteReg(0xB1, 0x09)
board.WriteReg(0xB2, 0xD0)
board.WriteReg(0xB1, 0x0A)
board.WriteReg(0xB2, 0x04)
board.WriteReg(0xB1, 0x0B)
board.WriteReg(0xB2, 0x1A)
board.WriteReg(0xB1, 0x0C)
board.WriteReg(0xB2, 0x06)
board.WriteReg(0xB1, 0x0D)
board.WriteReg(0xB2, 0x33)
board.WriteReg(0xB1, 0x0E)
board.WriteReg(0xB2, 0x21)
board.WriteReg(0xB1, 0x0F)
board.WriteReg(0xB2, 0x0A)

Carrie

Hello Trishala,

Lock does not matter for deserializer patgen.

Regards,

Carrie

Hi Carrie

I have a doubt I am attaching two files.. First read the doc file and then the spreadsheet file. In the doc file I have attached the qualcomm datasheet snippet where we have to calculate the settle count value with respect to the timing parameters. It has been observed that the Ths_prepare set in section7.4.21 in the datasheet is 121 and THS_zero is 134 but if we the qualcomm datasheet and the TI datasheet page no 16 the Ths_prepare must be between the 50ns to 100ns. Please go through the spreadsheet and the doc file that might help you to understand what I am trying to say.  ti936.docxQUALCOMMand TIsettle count.xlsx

Hello Trishala,

I am looking into this and will get back to you tomorrow.

Thanks,

Carrie

Hello Trishala

The timing parameters shouldn’t be a problem.

Verify that the CSI transmission data rate is 400 Mbps. Note that the data rate value is F_DATA in Mbps, and not F_TIMER (see the table on page 1 of the document you sent). If the data rate is actually 800 or 1600 Mbps, make sure to reset the timing parameters, program the correct data rate into CSI_PLL_CTL, and double the line rate to 0xC66.

Best regards,

Carrie

Hi Carrie

I found that the CSI clock rate rate is approximately 269.33Mhz instead of 200MHz then what would be the data rate as before I have mentioned that it was 200MHz that is why you have told us that it would be 400Mbps

Thanks

Trishala

Hello Trishala

Can you send more information about what you are seeing/not seeing on the SoC in terms of errors and CSI packets?

Additionally, the CSI clock rate and the data rate are two separate parameters. The data rates supported by the 936 are 400, 800, or 1600 Mbps and independent of the CSI clock rate. When I gave you the 400 Mbps value, that was because I thought that the value you sent me was the expected clock rate for incoming data, which determines data rate. If these are mixed up, this could be causing the issue. 

Regards,

Carrie

Hi Carrie

Sorry for the late reply. We were waiting for the serializer actually. We are actually using 913a  serializer. The FPDlink has been succesfuuly made. As discussed earlier you told us to try pattern generation from the serializer.. So what are the register configuration changes needed for the pattern generation through serializer. Please tell us is there any init setting required or not plus is there any change in the register configuration for the deserializer . We are using RAW10 mode instard of CSI-2 mode used earlier. The DT we are using is YUV422 .

Thanks

Trishala

Hello Trishala,

The 913A does not have a pattern generator feature. Is that the serializer that you're waiting for, or are you waiting for a different serializer?

Regards,

Carrie

Hi Carrie

913A is the serializer we were waiting for. I was looking with deserializer one which we are still not able to get the pattern generation. The errors we are getting from SOC. We have checked with the qualcoom team they have told us the data rate cab be 800Mbps as they always set the data rate to the maximum value.

1.  Lane 2 control error IRQ----- IRQ indicates illegal LP state transition such as LP01 not followed by LP0
2. Lane CLK control error

Thanks

Trishala

Hello Trishala,

Have you set the data rate to 800 Mbps (CSI_PLL_CTL[1:0] to 0b10) ? Make sure to reset the timing registers to their default settings. No configuration is needed for timing at 800 or 1600 Mbps. Make sure to set a line period of 0x0C66 in the pattern generator. If this isn’t working, please send the complete script that you are running and I will look it over.

Regards,

Carrie

Hi Carrie

As discussed before we have tried to connect 936 with 913A serializer there are some basic doubts which are facing.

1) Do the data type and the format needs to be same for the RAW 10 mode.

2)  Since we are using Qualcomm SOC : In the library file we found that they have configured certain registers while the sensor start streaming

0xb0--->0x1c
0xb1-----> 0x13
0xb2------->0x1f

Can you please describe this registers and is there a need to set these registers

Thanks

Trishala

Hello Trishala,

When 936 is paired with 913A in RAW10 mode, 936 register 0x70 controls the CSI-2 data type for the resultant output data. The default is 0x2B which corresponds to the MIPI CSI-2 data code for RAW10. 

As far as the 0xb0-0xb2 registers, those configurations should not be applied. Please remove those configurations and there is no need to adjust those registers. 

Best Regards,

Casey 

HI Casey

Can you also confirm one scenario do we need to configure HSYNC and VSYNC . when 936 is being paired with 913A. plus how to configure that .

Thanks

Trishala

Hello Trishala,

HSYNC and VSYNC are required when 913A is paired with 936 since 936 uses the sync signals to construct MIPI packet boundaries. This is described in the 936 datasheet section 7.4.14

Best Regards,

Casey 

Hi Casey

1) Can you tell me what is the reason that the PASS status will not be met. And without the pass status can we get the csi packets ?

2)the im.6 actually sends the bt656 8 bit data to serializer so from the deserializer  we have set 0x70 register to 0x1F i.e YUV422 10 bit format.. Will it work?

3) is there any relation with HSYNC and VSYNC

Thanks

Trishala