DS90UB953A-Q1: 'Multi-bit Error in SYNC Sequence - Uncorrectable'.

xinxin wang1

Part Number: DS90UB953A-Q1
Other Parts Discussed in Thread: DS90UB954-Q1

Application ：I am using DS90UB953A-Q1 to serialize mipi signals. The mipi signal is generated by xilinx FPGA mipi csi-2 tx ip core. The DS90UB954-Q1 is the deserializer used to receive serialized data from DS90UB953A-Q1 through an FPD-Link III interface. The xilinx FPGA mipi csi-2 rx ip core is used to analyze the mipi signal from DS90UB954-Q1.The lock and pass status of DS90UB954-Q1 is high.

I read the register of DS90UB953A-Q1. The value of register CSI_ERR_DLANE23 is '0x01000100'. It means 'Multi-bit Error in SYNC Sequence - Uncorrectable'. Do you know the reason of this error? There is no error in CSI_ERR_DLANE01.

Best Regards!

over 5 years ago

0 Steven(Shenzhen) Shi over 5 years ago

TI__Mastermind 30515 points

pls check if the 953's CSI2 setting is aligned with the video source in your system. For 953, it can support 2lanes or 4lanes with conituous or non-continuous clock.

regarsd,

Steven

0 xinxin wang1 over 5 years ago in reply to Steven(Shenzhen) Shi

Prodigy 80 points

Hello steven,

Yes, I have checked this. And I have read register '0x1C,0x5C - 0x60' of 953. No other errors was found.

Best Regards!

0 Steven(Shenzhen) Shi over 5 years ago in reply to xinxin wang1

TI__Mastermind 30515 points

how many lanes are set in 953? is it aligned with sensor output?

Steven

0 xinxin wang1 over 5 years ago in reply to Steven(Shenzhen) Shi

Prodigy 80 points

Both 4 lanes.

Best Regards!

0 Steven(Shenzhen) Shi over 5 years ago in reply to xinxin wang1

TI__Mastermind 30515 points

If your CSI2 port setting is correct, such as lane number, clock continuout / non-continous mode setting, but only Dlane2/3 has SOT error, it means the layout of lane2/lane3 could have issue.

regards,

Steven

0 xinxin wang1 over 5 years ago in reply to Steven(Shenzhen) Shi

Prodigy 80 points

The layout of lane2/lane3, did you mean the hardware design?

Is there any method to find the problem of the hardware design?

Best Regards!

0 Steven(Shenzhen) Shi over 5 years ago in reply to xinxin wang1

TI__Mastermind 30515 points

basically you can measure if the DPHY spec. of CSI2 transmitter is correct or not with MIPI analyzer.

from our chip, it can detect the DPHY input error in lane2/lane3 but lane0/1 has no error.

regards,

Steven

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DS90UB953A-Q1: 'Multi-bit Error in SYNC Sequence - Uncorrectable'.