where do you find TDD Min = 100ps?

Hi Zhou-san

the value of min 100ps is from following E2E session.

Thanks

Muk

in revision H datasheet, it shows 1/2ns, but somehow deleted in revision I. I need to check with design to confirm. 

Hi Zhou-san,

I wait your update for it.

Muk

Hi Zhou-san,

Do you have any update?

Muk

sorry, still try to get history of this device since it's more than 10 years.

we did measured Tcd/Tdd before, it's 1.2ns for min Tcd/Tdd

Hi Zhou-san,

Customer said, the customer test result with their board is under 1.2ns.....

Thanks

Muk

what is their data? but should not be 0

Hi Zhou-san,

I attached customer waveforms.

It is affected by reflected waves, but they appear to be less than 0.5ns for both DIR and NXT.

Could you please give me your comment?

DIR  / ch1:clock / ch2:dir

NXT / ch1:clock/ ch2:nxt

Customer is considering adding serial resistors to delay the waveform. Is there any problem?

Thanks

Muk

does customer use ZYNQ FPGA? if not, it should be fine.

Hi Zhou-san,

Could you please let me know the reason of "it should be fine"?

Is it no problem that they will not meet UTMI+ Low Pin interface(ULPI) Rev1.1? 

Also, could you please give me  your comment for below,

Customer is considering adding serial resistors to delay the waveform. Is there any problem?

Muk