We designed ethernet circuit using TI DP83867IRRGZ and Xilinx FPGA. PHY interface VDDIO =3.3V. The data sheet spec states RX_CLK signal voltage VoH = 2V (MIN), and VoL =0.6V (MAX). We used a scope to measure the RX_CLK signal, the scope screen shot is as follow:
The measured VoL = 1.3674V which is far above the spec value of 0.6V. We don't know if that is a cause of the failure of our Ethernet circuit.
Please advise.
Thanks,
Jimmy
Hi Cecilia,
We probed the signal at the end of 22 ohm serial resistor which is connected to RX_CLK pin of DP83867IR.
We just probe the RX_CLK signal again at the other end of the resistor, which at this time it is the output of RX_CLK signal directly from the PHY transceiver, as shown in follow screen shot
This time VoL = 0.6939V. It is still out of the spec value of 0.6V (MAX)
The XI oscillator signal is in following screen shot:
By the way, the probe is passive with 1Mohm impedance.
Jimmy
Hi Cecilia,
We use Keysight MSOS404A oscilloscope to measure the RX_CLK. and we could not observe the square waveform of RX_CLK signal although the scope has 4GHz bandwidth, and 20GS/S. Do you mind to let me know what kind of scope you use to observe the square waveform of RX_CLK?
We use PC ethernet port as a link partner to test our new designed GigE board. We have two similar designs, one uses TI DP83867IRPAP (64pin) device, the other uses DP83867IRRGZ (48pin) device. Under same test condition, the 64-pin one is successful to communicate with PC, while the 48-pin one fails to communicate with PC.
Then we use MSOS404A scope to do the trouble shooting and found out the 64pin device RX_CLK signal is within the spec (VoL = 0.479V), as shown in following scope screen shot:
While the 48-pin device RX_CLK clock is out of the spec (VoL = 0.735V), as shown in following scope screen shot:
We don't know what attribute to this RX_CLK signal out of spec since this signal is directly output from PHY to MAC. We made a comparison test between our two designs using the scope for other signals, including +3.3V, +2.5V, +1.1V (64pin)/+1.0V(48pin) and their power ramp sequence, 25MHz oscillator in and out of the device and CTX_CLK signal from MAC to PHY. And we did not observe difference among those signals.
Could you shed a light for us with regards to this 48pin device RX_CLK signal? Why its VoL out of spec (Spec value VoL =0.6V MAX)?
Thanks,
Jimmy
Hi Cecilia,
The 22 ohm resistor on RX_CLK signal is to match the source impedance, and reduce the reflection on the signal. It is originally on our 64-pin design.
We tried several series resistor values on 48-pin RX_CLK signal, including 0 ohm, the 22 ohm has the best signal in terms of waveform shape.
We have not probed the MDI signal using 100 ohm termination. We plan to do it.
The question is that why there is no valid PHY-ID available on our 48-pin design. My understanding about the PHY_ID is only relating to resistor strap config (RX_D0 and RX_D2) and power up sequence, which are all as expected. How critical of the reset signal is to latch the strap pins configuration to PHY register? Do you think following reset signal has an issue there?
We tested several 48-pin boards and the problem is the same, the RX_CLK pulse low voltage level is out of the spec.
Jimmy
Hi Cecilia,
Please find 64-pin reset signal above.
The reset circuit difference between 64-pin design and 48-pin design is that there is a voltage supervisor ship in our 64-pin design. While in our 48-pin design, we remove the voltage supervisor chip in the consideration of board space. Do you think that has an issue in reset signal?
I will capture scope shot of reset signal, and two strap pin signals and send it to you later.
Jimmy
Hi Cecilia,
64-pin board power up sequence and reset signal is as follow:
The 64-pin board strap and reset signal is below:
The 48-pin board strap and reset signal is below:
Based on waveform comparisons between 64-pin board and 48-pin board, there is no issue stand out in terms of PHY-ID latch up. We don't know why on 48-pin board, we could not get available PHY_ID?
Jimmy
Hi Cecilia,
We add a 10uf cap on the top of 48-pin reset cap C10 to delay the reset high signal, as shown in following scope shot:
However, the PHY-ID address on 48-pin board is still unavailable. Any trick to get a valid PHY_ID at powerup on TI DP83867IR PHY chip?
Jimmy
Hi Cecilia,
It is marked wrong in slide. The signal is the PHY clock output on pin 18 of 48-pin design. I rescope it on 48-pin design board now, as below
In our original 48-pin design, there is no reset chip in reset circuitry. A reset chip is added to 48-pin board later, which address the powerup reset delay and more aligned with 64-pin design. Please see the attached file which shows the difference before and after the reset chip is added.
VMIO3.3V.docxPlease let me know if you have further question about those scope traces.
Thanks,
Jimmy
Hi Cecilia,
The serial cable (three wires, RX, TX, GND) is attached to 48-pin board as shown in above picture. While PHY register values are dumped via SMI bus using the SW tool developed by our SW team, we have to use Xilinx SDK environment to get the PHY register values, which is the reason we made this kind of test.
REgards,
Jimmy
