DS125DF111: about output Clock

Dear Nasser;

I have confirmed to set 0x1E[7:5] t0 011 or 010,The output pin is still data.

If it doesn't support this. Do TI have any other IC support clock recovery and Data rate support  1.25Gbps~11.3Gbps?

Regards.

Dear Nasser;

1). I reconfirmed DS125DF111,output the internal 10 MHz clock is ok,but can't output Q and I Clock;

10MHz clock output seting:

WIIC 0x30 0xff 0x05
WIIC 0X30 0X09 0X20
WIIC 0X30 0X1E 0XA0

result is a clock 9Mhz

Q-clock output seting:

WIIC 0x30 0xff 0x05
WIIC 0X30 0X09 0X20
WIIC 0X30 0X1E 0X60

result is a voltage 1.5V

I-clock output seting:

WIIC 0x30 0xff 0x05
WIIC 0X30 0X09 0X20
WIIC 0X30 0X1E 0X40

result is a voltage 1.5V

other question,what is Q and I clock?The clock come from input Data? 

2) I don't have DS125DF410,now.

Regards.

Greeting:

I have DS110DF410,I checked the DS,I/Q clock functions is the same with DS125DF410,I will test DS110F410 as soon as possible

Best regards!

Greetings,

I've  tested DS110DF410,There is a signal input, but can't output the Q-clock,what's the setting wrong?Can you hele me?

This is setting file

Q-clock.cfg

Regards,, 

Dear Nasser,

I'm sure  there is a singal locked in channel 0,the Locked LED is on and Reg 0x02=0xDC

I have tested set Reg 0x09[7:0]=0x20 or 0x09[7:0]=0x49, 0x1E[7:0]=0x49,but can't output the clock

Is there any other Reg need to setting?

Hi Nasser

Do you have any other suggestions about output the Q/I clock?

Best regards!

Greetings,

We have tested it again, input data rate  is 1.25Gbps and pattern is PRBS 7/23/31;

There is a video, in the video 8 seconds before we set output 10M clock is ok and last two seconds we set output I‘clock is fail

There is any picture/video/log about the test, We can't find out what's wrong

1E-49.cfg

1E_40.cfg

This picture is test DS110DF410 output  The eye diagram

Best regards..

Dear Nasser:

Do you have the cfg file which is generate the recovered clock in the lab?

We want to load it and check whether there is some settings is different

Regard.

Greetings,

You tested input data is 10Gbps or 1.25Gbps?

If the input data is 1.25Gbps, is the output clock 1.25Ghz or 10Ghz? We need to output 1.25Ghz clock, is the IC supported? If not, is there any other IC to divide the clock by 8?

Regards!

Hi Nasser,

The IC is very perfect,but we still haven't found out the problem about us.

We need more informatin,As follows

1. We think the extract clock functions DS125DF410 is same to DS110DF410,so,we tested IC is DS110DF410,and you?

2.Does it mean that the input signal is 10.3125Gbps ,either at 1.289Ghz or 10.3125G clock can be output? What are the register settings different for the two Freq clock?

3.Can you share more detailed information about conditions, steps,methods,pictures,video and more?

The more the better,We will try our best to find out our problems.

Thank you very much!

Greetings,

Can it setting up the clock amplitude?

Hi Nasser,
Thank you very much!We have solved the problem.
There are some other questions about the retimer.
1) The retimer start with standard mode "Ethernet", is there a way for it to automatically switch modes based on the input data.for example,when the input data is 1.25Gbps auto switch to "Ethernet" and input data is 9.953Gbps auto switch to SDH/SONET.If not,How to setting the Retimer start with SDH/SONET after power off.
2) There are 4 Pins indicating the locked state, Is there a function to assert signal detect?
3) We want to the i-clock divider by 2(4 or 8 is ok).for example 10.3125Gbps data recovery 10.3125Ghz clock,we want the i-clock is 5.51625Ghz (2.278125Ghz or 1.289Ghz is ok) and the clock must synchronize with input data.
4)earlier,you shared the Recovery 10Ghz clock,We noted the clock amplitude is only 130mVp-p, How to increase the amplitude through registers(compensation for high loss)？

Best Regards..