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Original question:

DS90UB960-Q1: Possible reasons for register 0x7a/0x7b

DS90UB960-Q1: Performing cable margin analysis from within custom Linux device driver

Charles Notley
Prodigy 40 points
Part Number: DS90UB960-Q1
Other Parts Discussed in Thread: DS90UB954-Q1

The Application Report SNLA301–January 2019 titled "Margin Analysis Program (MAP) and strobe positions for DS90UB954-Q1 and DS90UB960-Q1" describes manual strobe settings in section 5.2.1 STROBE_SET Register, page 22.  It specifies that manual control should not be used unless other adaption modes are disabled (0x42[0] = 0 and 0x40[0] = 0).  The data sheet shows that register 0x40 is a reserved register and there's no description of what setting/clearing bit 0 does.  I would like to know what it does.

  • 0
    TI__Genius 11340 points

    Hi Charles,

    0x42 AEQ_CTL         AEQ Control
        7 reserved R 0 Reserved
        6:4 AEQ_ERR_CTL RW 0x7 AEQ Error Control
    Setting any of these bits will enable FPD3 error checking during the Adaptive Equalization process.  Errors are accumulated over 1/2 of the period of the timer set by the ADAPTIVE_EQ_RELOCK_TIME filed in the AEQ_TEST register.  If the number of errors is greater than the programmed threshold (AEQ_ERR_THOLD), the AEQ will attempt to increase the EQ setting.  The errors may also be checked as part of EQ setting validation if AEQ_2STEP_EN is set.  The following errors are checked based on this three bit field:
    [2] FPD3 clk1/clk0 errors
    [1] DCA sequence errors
    [0] Parity errors
        3 AEQ_SFIL_ORDER RW 0 AEQ SFILTER Adapt order
    This bit controls the order of adaption for SFILTER values during Adaptive Equalization.
    0 : Default order, start at largest clock delay
    1 : Start at midpoint, no additional clock or data delay
        2 AEQ_2STEP_EN RW 0 AEQ 2-step enable
    This bit enables a two-step operation as part of the Adaptive EQ algorithm.  If disabled, the state machine will wait for a programmed period of time, then check status to determine if setting is valid.  If enabled, the state machine will wait for 1/2 the programmed period, then check for errors over an additional 1/2 the programmed period.  If errors occur during the 2nd step, the state machine will immediately move to the next setting.
    0 : Wait for full programmed delay, then check instantaneous lock value
    1 : Wait for 1/2 programmed time, then check for errors over 1/2 programmed time.
    The programmed time is controlled by the ADAPTIVE_EQ_RELOCK_TIME field in the AEQ_TEST register
        1 AEQ_OUTER_LOOP RW 0 AEQ outer loop control
    This bit controls whether the Equalizer or SFILTER adaption is the outer loop when the AEQ adaption includes SFILTER adaption.
    0 : AEQ is inner loop, SFILTER is outer loop
    1 : AEQ is outer loop, SFILTER is inner loop
        0 AEQ_SFILTER_EN RW 1 Enable SFILTER Adaption with AEQ
    Setting this bit allows SFILTER adaption as part of the Adaptive Equalizer algorithm.

    0x40 SFILTER_CTL         Dynamic SFILTER control
        7 SFIL_ALWAYS_ON RW 0 Enable SFILTER Always
    Setting this bit allows SFILTER adaption at all times, including prior to lock.  This bit overrides the SFIL_ADAPT_MODE setting.
    1 : SFILTER adaption is always enabled
    0 : SFILTER adaption only after locked (based on SFIL_ADAPT_MODE setting)
        6 SFIL_MEAS_ONLY RW 0 Enable SFILTER Measurement only
    Setting this bit allows SFILTER circuit to take measurements, but not update the SFILTER delay settings.
    1 : Measurements only
    0 : Allow adaption of SFILTER settings
        5:4 SFIL_THRESH_CTL RW 0 SFILTER Threshold Control:
    Sets the threshold for incrementing or decrimenting the SFILTER.
    00 : Use programmed threshold in SFIL_THRESHOLD register (default is 0)
    01 : 60% ratio of early vs late
    10 : 1/2 of previous opposite change (hysteresis)
    11 : equal previous opposite change (hysteresis)
        3:2 SFIL_SMPL_SIZE RW 0 SFILTER Sample Size:
    Sets the sample size in FPD3 clocks for the SFILTER adaption routine.
    00 : 256 samples
    01 : 512 samples
    10 : 1024 samples
    11 : 2048 samples
        1 SFIL_ADAPT_MODE RW 0 SFILTER adapt mode:
    This bit controls when SFILTER adaption is activated.  If set to 0, adaption will begin as soon as the clock recovery circuit indicates the frequency is locked.  If set to 1, adaption will wait until the AEQ adaption is complete.
    1 : Wait for AEQ adaption complete
    0 : Adapt after clock is locked
        0 SFILTER_EN RW 0 Enable Dynamic SFILTER adaption:
    Setting this bit enables dynamic adaption of the SFILTER clock and data delays.
    1 : Enable SFILTER adaption
    0 : Disable SFILTER adaption
  • 0 in reply to Jiashow Ho
    Prodigy 40 points

    I did not find this register described anywhere in the datasheet.  Where did you find this information?

  • 0 in reply to Charles Notley
    TI__Genius 11340 points

    Hi Charles,

    We have this information internally.

    Jiashow