DS90UB960-Q1: Configure serializer to make the sensor exit SLM

Hi Jiashow,

The SLM entry/exit phases are performed in D-PHY level, namely there is a certain way in which the data on the lanes should look like in order to enter or exit SLM state. The SoC implements the D-PHY and assuming the driver will require entering/exiting to/from SLM mode, it will modify the levels of the line.

The SerDes handles all I2C commands but I don't know if it handles things in the D-PHY level, specifically, related to the SLM.

My question is - is there any handling in the SerDes, related to SLM or only I2C command are transferred?

Thanks,

Matan

Hello Matan,

I think there is some misunderstanding here in the system level implementation. First, 953 and 960 use CSI-2 version 1.3, not 3.0. But the SLM section you referenced is the same between those two documents. However SLM is between MIPI CSI-2 source and CSI-2 sink directly. In that case it would be between imager source to 953 sink or 960 source to SoC sink. SLM ULPS commands do not propagate across the link from imager to 960. 

What is the system level goal here? To trigger 960 provide the ULPS command to the SoC? 

Best Regards,
Casey 

Hi Casey,

Thanks for the clarifications. I will rephrase my questions.

In the case the CSI-2 SINK side "decided" to put the CSI-2 link into SLM - it may be triggered by an external signal to the CSI-2 SINK, or by CCI command - in order to get the CSI-2 link into ULPS.

1. For the SLM entry phase, only the TX side enters SLM and then propagates the ULPS to the CSI-2 SOURCE by sending ULPS command on each lane - is it supported in the SerDes? Namely, will the 953 will propagate the ULPS command to the 960 and then to the SOC?

2. For the SLM exit phase - when the 953 will wake-up the camera? Will the 953 wake up the camera once any change on SDA/SCL lines, between the SOC and 960, will be detected ? Will the 953 will wake up the camera once specific wake-up sequence on I2C lines, between the SOC and the 960, will be detected? Other?

I hope I managed to explain myself better.

Thanks,

Matan

Hello Matan,

The flow described above is not exactly supported in this way through the CSI-2 interface but I think we can provide some alternative options on how to handle power on/off conditions related to the imager, serializer, deserializer, and SoC. Please give us a couple of days to put together amore thorough explanation 

Best Regards,

Casey 

Hi Casey,

Thanks for your answer.

Just to correct my typos from my questions:

In the case the CSI-2 SOURCE side "decided" to put the CSI-2 link into SLM - it may be triggered by an external signal to the CSI-2 SOURCE , or by CCI command - in order to get the CSI-2 link into ULPS.

For the SLM entry phase, only the TX side enters SLM and then propagates the ULPS to the CSI-2 SINK - in this case the 953, by sending ULPS command on each lane - is it supported in the SerDes? Namely, will the 953 will propagate the ULPS command to the 960 and then to the SOC?

I will wait for the thorough explanation.

Thanks,

Matan

Hi Jiashow,

SLM is defined between the CSI-2 SINK and the CSI-2 SOURCE in the D-PHY level.

When implementing with SerDes, the 960 and the 953 are in-between, implementing "their own D-PHY" to communicate with the SoC and the camera sensor.

So my questions refer to the operations which are not standard CCI or HS/LP operations. SLM exit phase is one of those cases which are not standard as there is certain pattern of the lines' levels.

Thanks,

Matan