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TPS65987D: TPS65987 inrush current time out setting in PDO negotiation

Part Number: TPS65987D
Other Parts Discussed in Thread: TPS65987

Hi all,

 We see OCP threshold description on slva994.pdf as below fig.

 Is it possible to disable FW OCP threshold between T1 and T2 in power source application? We have many compatible issues about inrush current when 20V PDO is initiated.  IoC (peak current set in 0x32?) is not a a good setting for this condition because this peak current is larger than normal OCP point customer hope.

 Thanks for your kindly help. 

Regards,

Gary Teng

 

  • Add the picture.

    Gary

  • Hi Gary,

    No it is not possible to disable FW OCP threshold between T1 and T2 in power source application. 

    Do you have an EC on your system that can write I2C messages to the PD controller?

  • Hi Adam,

     Most docking products have EC (DMC?) to control their system. Can they set something by 4cc / I2C at PDO start up?

     I see "External Power Path Over-Current timeout" setting in REG 0x28. Can we use it to solve the inrush current issue?

    Regards,

    Gary

  • Hello Gary,

    I was going to make the recommendation to use the ‘SRDY’ 4cc command but that would not work in your case because the TPS65987D is acting as the source.

    The only thing I can suggest is if your system is only required to act as a source, you can connect the two internal power paths in parallel to one another. This would reduce the amount of current flowing through an individual power path which should reduce the likely hood that an OCP event occurring. This is called power duo mode for the TPS65987. You can reference the USB-C-PD-DUO-EVM on how to properly implement this into your system. 

    This is the only thing I can suggest as it is not possible to disable FW OCP threshold between T1 and T2 in power source application