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SN65DSI83: I want to know the specific settings of SN65DSI83.

Part Number: SN65DSI83
Other Parts Discussed in Thread: DSI-TUNER,

Dears

I have a question. Details are shown in the attachment.

Q1 What should I enter for DSI_HPW, DSI_HBP, DSI_HFP, DSI_VPW, DSI_VBP, DSI_VFP?

Q2 What should I enter for CHA_SYNC_DELAY_LOW and CHA_SYNC_DELAY_HIGH?

Sincerely,

2350.question.pdf

  • Hi Sakai-san,

    You can reference this training video: https://training.ti.com/configuring-sn65dsi8x-single-channel-dsi-single-link-lvds-operation 

    The DSI-Tuner will automatically populate the SYNC_DELAY registers

    Regards,

    I.K.

  • Dear I.K.
    Thank you for your reply.
    I watched the video. I'm asking a question because I didn't fully understand the settings.
    Q1 What should I enter for DSI_HPW, DSI_HBP, DSI_HFP, DSI_VPW, DSI_VBP, DSI_VFP?
    Q2 What should I enter for CHA_SYNC_DELAY_LOW and CHA_SYNC_DELAY_HIGH?
    >>I check with dsi-tuner.
    additional
    Q3 Is there a problem with my system?
    Sincerely,
  • Q1 You should enter the same thing you did for the LVDS side

    Q2 The DSI-Tuner will enter this for you

    Q3 Looking at your attachment, you stated "I think the number of NOPs will change for each LINE." This is not correct for the SN65DSI83. The DSI input (active pixels, blanking pixels, clock frequency) should be constant and stable.

    Regards,

    I.K.

  • Dear I.K.

    Thank you for your reply.

    I am a beginner with no experience using MIPI D-PHY and DSI.

    I understand that:

    ◆My Processor
    (1) MIPI TX has a DSI layer and a D-PHY layer.
    (2) The DSI layer is 2200x1125 24bit 60fps, so the bandwidth is 3.564Gbps.
    (3) The D-PHY layer has more bandwidth, 3.6 Gbps.
    (4) Since the bands of the DSI layer and the D-PHY layer are different,
    There is a gap between the packets to be forwarded.
    (5) Of course, the active pixels and blanking of the DSI layer are the same.
    Q1
    Is there anything wrong with the above idea?
    Please let me know if there is something wrong.
    Q2
    With the above idea, is there anything I have to do on the Processor side to connect with the SN65DSI83?
    Q3
    Regarding (4). Why does GAP absorb it? For example, should I transition to LP mode?
    (I want to know the exact answer.)
    Sincerely,
  • Dear I.K.

    I asked a question, but I haven't received an answer yet.

    Please reply as soon as possible.
    Sincerely,
  • Hi Sakai,

    Sorry I missed your follow-up. It would be better if you kept all your questions to one thread. 

    As for your questions, I cannot speak on how your MIPI TX works, only on what the SN65DSI83 is expecting on the input. The SN65DSI83 is expecting the input on it's DSI lanes to be stable and constant (active pixels, blanking pixels, clock frequency). You then only have to connect it in accordance with the initialization sequence in the datasheet.

    Regards,

    I.K.