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SN65DSI86: Please check our setting

Delo Lee
Prodigy 105 points
Part Number: SN65DSI86
Other Parts Discussed in Thread: DLPC3433

Hi Sir,

Below is the MIPI DSI input timing.

and below is the DP output timing we need.

Please help check our registers setting. if any wrong please let me know. thanks~

function dsi86_sw_reset()
{
log -t wo_calib "dsi86_sw_reset"
i2cset -y 12 0x2d 0x09 0x00
i2cset -y 12 0x2d 0x0d 0x00
}

function dsi86_2560_720_CLK_SRC_EXT()
{
log -t wo_calib "dsi86_2560_720_CLK_SRC_EXT"
i2cset -y 12 0x2d 0x0A 0x06
i2cset -y 12 0x2d 0x0D 0x00
i2cset -y 12 0x2d 0x10 0xA0
i2cset -y 12 0x2d 0x11 0x00
i2cset -y 12 0x2d 0x94 0x80
i2cset -y 12 0x2d 0x0D 0x01
##======Enable ASSR in Panel ======
i2cset -y 12 0x2d 0x64 0x01
i2cset -y 12 0x2d 0x74 0x00
i2cset -y 12 0x2d 0x75 0x01
i2cset -y 12 0x2d 0x76 0x0A
i2cset -y 12 0x2d 0x77 0x01
i2cset -y 12 0x2d 0x78 0x81
sleep 0.02 ##20ms
##======Enable enhanced frame and ASSR in DSI86 ======
i2cset -y 12 0x2d 0x5A 0x05
##======Number of DP lanes ======
i2cset -y 12 0x2d 0x93 0x20
i2cset -y 12 0x2d 0x95 0x00
i2cset -y 12 0x2d 0x96 0x0A
sleep 0.02 ##20ms
i2cset -y 12 0x2d 0x20 0x00
i2cset -y 12 0x2d 0x21 0x05
#i2cset -y 12 0x2d 0x22 0x00
#i2cset -y 12 0x2d 0x23 0x05
i2cset -y 12 0x2d 0x24 0xD0
i2cset -y 12 0x2d 0x25 0x02
i2cset -y 12 0x2d 0x2C 0x28
i2cset -y 12 0x2d 0x2D 0x00
i2cset -y 12 0x2d 0x30 0x05
i2cset -y 12 0x2d 0x31 0x00
i2cset -y 12 0x2d 0x34 0xDC
#i2cset -y 12 0x2d 0x35 0xB8
i2cset -y 12 0x2d 0x36 0x14
i2cset -y 12 0x2d 0x38 0x70
i2cset -y 12 0x2d 0x3A 0x05
##===== DP-18BPP Disable ======
i2cset -y 12 0x2d 0x5B 0x00
##===== Color Bar Disable ======
i2cset -y 12 0x2d 0x3C 0x00
i2cset -y 12 0x2d 0x3D 0x00
i2cset -y 12 0x2d 0x3E 0x00
i2cset -y 12 0x2d 0x09 0x01
##===== Enhanced Frame, ASSR, and Vstream Enable ======
i2cset -y 12 0x2d 0x5A 0x0D
}

  • 0
    Prodigy 105 points
    Hi Sir,
    I cannot see the picture in last post. so I add a attached file for timing spec.

    SN65DSI86 timing.docx

  • 0 in reply to Delo Lee
    TI__Guru**** 177396 points

    Hi,

    It looks like you are programming the DSI86 Video Registers with the DSI interface video timing. You should program the DSI86 Video Registers with the Video format that is expected to be displayed on the eDP panel. 

    If I looked at the HBP for the DP timing, it is decimal 440 which is hex 0x1B8. This is outside the DSI86 Video Registers programming field, is this the correct timing value? Do you have the actual EDID of the panel?

    There is a spreadsheet being created for the DSI86 Video Registers which you can use to generate the programming value, it is available at 

    Thanks

    David

     

  • 0 in reply to David (ASIC) Liu
    Prodigy 105 points

    SN65DSI86_PANEL_VIDEOREGISTER_CALC.zipHi David,

    I think we need MIPI DSI's HBP is 220 of dual channel mode(CHA and CHB), and DP output is HBP = 440.

    So, If we set the HBP of CHA to 220 and dual channel mode.

    Does it mean that the HBP of CHB is the same as CHA and the value is 220.

    Attached file is our setting.

     

    Thanks for your help!

  • 0 in reply to David (ASIC) Liu
    Prodigy 105 points

    8765.SN65DSI86 timing.docxHi David,

    About the MIPI DSI to DP => DP to MIPI DSI video signal path, you can reference attached photo.

    The MIPI DSI timing is for Qualcomm SD835 and TI's DLPC3433

    DP timing is for Lontium LT7911D

  • 0 in reply to Delo Lee
    TI__Guru**** 177396 points

    Hi,

    The issue here is the DP timing, especially the back porch value. If the back porch is decimal 440, then this is larger than the DSI86 video timing register bit field and this particular panel can't be supported by the DSI86.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 105 points

    Hi David,

    Do you mean DP's HBP = CHA MIPI DSI HBP??

    And the Max. value is 255(Hex is FF), right?

    Why it is not CHA HBP +CHB HBP in Dual channel DSI Left/right mode?

    Thanks~

    Delo

  • 0 in reply to Delo Lee
    TI__Guru**** 177396 points

    Delo

    The DSI86 will use the parameters in its Video Registers to determine the DisplayPort MSA parameters that are transmitted over DisplayPort every vertical blanking period. These MSA parameters are used by the eDP panel to recreate the video format provided on the DSI interface. So we should look at the eDP panel spec. 

    The issue here is that the HBP is 440, this is larger than the maximum value can be programmed in register 0x34. 

    When configured for dual DSI channels, the DSI86 will use VSS, VSE, and HSS packets from channel A. The DSI86 will use channel A events to recreate the same timings on the DisplayPort interface. The VSS, VSE, and HSS packets from channel B are used to internally align data on channel B to channel A.

    Thanks

    David