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Dear TI Team,
I have bought two DP83TG720EVM-MC Media Converter Evaluation Module Boards and I'm trying to build a network bridge with them.
Here is a block diagram of my setup:
I want to transfer tcp/ip data from PC#1 over single pair ethernet to PC#2. Therefor I want to use the two eval-boards to make the conversion from RJ45 to SPE and back from SPE to RJ45 again.
With the default configuration of the boards I didn't get a link up with the two eval-boards directly connected over SPE. So i changed the jumper J2 from one board from master to slave and now I get a stable link over SPE. I also have a link from both PCs to the respective eval-board but I cant transfer any data from PC#1 to PC#2.
When I directly connect PC#1 and PC#2 over RJ45 I can transfer data without problems.
I have read out the debug information from both eval-boards:
Board1:
Board: DP83TG720-Q1 Media Converter Board Revision: 4 RGMII DIP Switch position: SW1:1 SW2:1 SW3:1 SW4:1 Mode: 15 Schematic Revision: 4 R Software Revision: 2.4 PHY Type 1: DP83867E PHY ID: 0 PHY Revision: 1 PHY Type 2: DP83TG720 PHY ID: 8 PHY Revision: 4 ========== Complete status report ======== +------ General status of 720 PHY -------+ | - 720 PHY is MASTER | | - 720 PHY receiver valid link | | - 720 PHY remote receiver valid link | +------ General status of 867 PHY -------+ | - 867 PHY is SLAVE | | - 867 PHY receiver OK | | - 867 PHY remote receiver OK | +-------- Link status of 720 PHY --------+ | - Link is UP | +-------- Link status of 867 PHY --------+ | - Link is UP | | - Link is FULL DUPLEX | +------ Interrupt status of 720 PHY -----+ | - UNDER_VOLT_INTERRUPT DISABLED | | - OVER_VOLT_INTERRUPT DISABLED | | - OVER_TEMP_INTERRUPT DISABLED | | - LINK_STATUS_CHNG_INT DISABLED | | - LINK_QUALITY_LOW_INTERRUPT | | - ENERGY_DETECT_INTERRUPT | | - ESD_EVENT_INTERRUPT | |----- Interrupt status of 867 PHY ------| | - PAGE_RECEIVED_INTERRUPT | | - AUTONEG_COMP_INTERRUPT | | - LINK_STATUS_CHNG_INTERRUPT | | - FALSE_CARRIER_INTERRUPT | | - MDI_CROSSOVER_CHNG_INTERRUPT | | - XGMII_ERROR_INTERRUPT | | - POLARITY_CHNG_INTERRUPT | +----------------------------------------+
Board2:
Board: DP83TG720-Q1 Media Converter Board Revision: 4 RGMII DIP Switch position: SW1:1 SW2:1 SW3:1 SW4:1 Mode: 15 Schematic Revision: 4 R Software Revision: 2.4 PHY Type 1: DP83867E PHY ID: 0 PHY Revision: 1 PHY Type 2: DP83TG720 PHY ID: 8 PHY Revision: 4
========== Complete status report ======== +------ General status of 720 PHY -------+ | - 720 PHY is SLAVE | | - 720 PHY receiver valid link | | - 720 PHY remote receiver valid link | +------ General status of 867 PHY -------+ | - 867 PHY is SLAVE | | - 867 PHY receiver OK | | - 867 PHY remote receiver OK | +-------- Link status of 720 PHY --------+ | - Link is UP | +-------- Link status of 867 PHY --------+ | - Link is UP | | - Link is FULL DUPLEX | +------ Interrupt status of 720 PHY -----+ | - UNDER_VOLT_INTERRUPT DISABLED | | - OVER_VOLT_INTERRUPT DISABLED | | - OVER_TEMP_INTERRUPT DISABLED | | - LINK_STATUS_CHNG_INT DISABLED | | - LINK_QUALITY_LOW_INTERRUPT | | - ENERGY_DETECT_INTERRUPT | | - ESD_EVENT_INTERRUPT | |----- Interrupt status of 867 PHY ------| | - PAGE_RECEIVED_INTERRUPT | | - AUTONEG_COMP_INTERRUPT | | - LINK_STATUS_CHNG_INTERRUPT | | - FALSE_CARRIER_INTERRUPT | | - MDI_CROSSOVER_CHNG_INTERRUPT | | - XGMII_ERROR_INTERRUPT | | - POLARITY_CHNG_INTERRUPT | +----------------------------------------+
I can't see any problems in the debug information.
Can you please help to determine the problem of my setup.
Thank you!
Best regards,
Peter
Hi Peter,
Can you try sending data from PC#1 to one of the DP83TG720 Eval boards and setting the DP83TG720 in analog loopback mode? If that does not work, try setting the DP83867 in reverse loopback mode on the Eval board. This can help us determine the root cause of the data communication failure.
Regards,
Adrian Kam
Hi Adrian,
I set the DP83TG720 as instructed to analog loopback mode by setting register 0x0016=0x0008 and 0x0405=0x2800.
PC#1 (QuantaCo_14:21:a1) now sends a broadcast message asking for ip 192.168.0.255 and as expected a broadcast message comes back from the eval board (c4:44:44:04:01:81) but with the ip 192.136.0.255.
Looks like the ip gets changed by the eval board.
Next I set the DP83867 to reverse loopback by setting register 0x0000 to 0x5140 and 0x0016 to 0x0020.
With this change I don't receive any broadcasts anymore.
After that I changed the ip of my PC#1 to 10.0.0.2 and tried to ping 10.0.0.3 with the following result:
I would except to get the same arp broadcast message back that I sent out.
Best regards,
Peter
Hi Peter,
Can you confirm that it is indeed the DP83867 (device closest to PC #1) where you are not receiving a broadcast message back? In addition, can you try adding the second eval board, setting the DP83TG720 on the second eval board to loopback mode, and sending data to see if you get data back?
Regards,
Adrian Kam
Hi Adrian,
yes I can confirm after setting the DP83867 to loopback mode with PC#1 ip=192.168.2.255 I didn't receive broadcasts.
Then I changed the ip to of PC#1 to 10.0.0.2 and I received packets but not the broadcasts I transmitted.
As advised I set the DP83TG720 on eval board #2 to reverse loopback mode so that all data sent from PC#1 should be transmitted back over SPE to eval board #1 and then to PC#1 with the same result.
I get a broadcast message back but the data is not the same as transmitted by PC#1:
Its the same behaviour as when I set the DP83TG720 on eval board #1 into loopback.
Looks like the data gets corrupted.
Best regards,
Peter
Hi Adrian,
I found out that the setting for RGMII_DELAY_CTRL (Address = 0x602) on the DP83TG720 is not correct set.
The setting of the register is 0x0000 which set rx_clk and rx_data on the rgmii interface to be aligned but the setting should be 0x0002 so that data and clk are 90° phase shifted.
I changed the setting manually and now the transmission works fine.
With the wrong setting the data bits are sampled on the edge (during change) which causes wrong bit information sometimes.
I would recommend that you change the MSP430 Firmware accordingly that the register is correct initalised in future.
Best regards,
Peter
Hi Peter,
Thanks for letting us know about the RGMII_DELAY_CTRL register setting. We will review this internally.
Regards,
Adrian Kam