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Original question:

SN65DSI83: Regarding SYNC_DELAY

SN65DSI83: Regarding VS and HS output to LVDS

user6438649
Intellectual 400 points

Part Number: SN65DSI83

Dear I.K.

Regarding VS and HS output to LVDS.
I want to know how to generate VS and HS.
I think as follows.
VS signal
1.Asserted from HI to LOW by finding VSS.
2.Deasserted from LOW to HI by the setting value of VSYNC_PULSE_WIDTH register.
I especially want to make sure that "VS is asserted from HI to LOW only by finding VSS."

HS signal
1.Asserted from HI to LOW by finding HSS.
2.Deasserted from LOW to HI by the setting value of HSYNC_PULSE_WIDTH register.
I especially want to make sure that "HS is asserted from HI to LOW only by finding HSS."
Sincerely,
  • 0
    TI__Mastermind 35130 points

    Your understanding is correct. VS is signaled for a programmable number of lines, and it is asserted when HS is asserted for the first line of the frame. VS is de-asserted when HS is asserted again after the number of lines programmed has been reached. 

    Regards,

    I.K.