DS90UB941AS-Q1: schematic review of 941/936 in Cluster

Hi Betty,

For 941as, 

1. You have two 25MHz clock attached to REFCLK0 and REFCLK1. In external clocking mode is used, the two clock frequency should be the PCLK of the videos. Could you double check if 25MHz is the target PCLK? 

2. In Layout, please make sure the smaller power decoupling cap is placed close to the device.

3. On PDB pin, there's a 10k pull down resistor, please put an 10uF cap as well in parallel and make sure the SoC can drive the pin high. 

4. The mode_sel resistor ratio doesn't match selected modes. Please double check again datasheet. 

5. IDX resistors is correct in the schematic but not correct in the table below IDX circuit.

For 936,

1. Please use decoupling cap values from the datasheet for VDD18 rails.

2. Please double check PDB pin connection. Currently there is a 10k pull up and a 10k pull down. It should have been a 33k pull up and 10uF cap to GND.

3. The IDX table is incorrect. Current IDX strap the device into 7 bit 0x30.

Best Regards,

Charley Cai