DP83640T-EVK: align DP83640 CLK_OUT phase from master 83640 to slave 83640? (AN-1729)

Hello,

We are looking into this issue and will provide feedback by Monday.

Thank you,

Nikhil

Hello,

Devices should be set to Master or Slave mode upon bootup. The Slave device will become synchronous to the Master device.

To answer your questions:

Two DP83640-EVKs, one set for master, one set for slave, connected with a CAT-5 cable is enough to repeat this experiment. CLK_OUT must be enabled (Register 0x1C). Enabling Synchronous Ethernet mode in register 0x1C may be done for the slave device. I will look into if this is required. 

Please let me know if you have any further questions.

Thank you,

Nikhil 

Hi Nikhil, 

Thanks for the reply. I can confirm that I set one board for master and another for slave by adjusting MII MODE SELECT and RMII MASTER ENABLE jumper. CLK_OUT was also enabled. In this setup, if Synchronous Ethernet mode was enabled, the relative phase of the signals was fixed. But this phase highly depends on the time of enabling, i.e., the phase varied every time when mode was reset and enabled again.  While Synchronous Ethernet mode was disabled, two signals were not synchronized at all. 

So, in either case, I was not able to align the phase properly between two signals by following AN-1729 tutorial. It seems that I clearly missed some crucial step. So would you mind elaborating more specifically on what is the procedure for synchronization and phase alignment step by step please? I really appreciate it. 

 In addition, according to SNLA100, section 6 (Synchronization Measurement Setup), each DP83640 Demo Card was connected with master or slave system for testing. So what is providing Ethernet MAC if I just use two DP83640-EVKs or I just simply do not need MAC in this experiment? Thanks.

Regards,

Cheng

Hi Cheng,

I am working in the same team as Nikhil. He is out of office currently but he will get back to you by Tuesday next week.

-Regards

Aniruddha

Hi Cheng,

For this experiment, you should not need to connect an Ethernet MAC. The following procedure can be used:

1. Write 0x0000 to PHYCR2 (Page 0 Reg 0x1C) in Master DP83640 to enable CLK_OUT

2. Write 0x2000 to PHYCR2 (Page 0 Reg 0x1C) in Slave DP83640 to enable CLK_OUT and Enable Synchronous Ethernet.

3. Write 0x8019 to PTP_COC (Page 6 Reg 0x14) in both DP83640 , set CLK_OUT as 10MHz. Note that 0x19 is 25 decimal, to divide the 250 MHz clock by 25. 

4. Write 0x0004 to PTP_CTL (Page 4 Reg 0x14) in both DP83640 , Enable PTP 1588.

5. Take 100 samples of the CLK_OUT phase error.

6. Enable the Event monitor and get the event timestamp:

6a. Write 0x1C0F to the PTP_EVNT register. This first write sets up a single event capture for CLK_OUT/GPIO12 with Event 7 (though any event may be used). 

6b.Write 0x5C0F to the PTP_EVNT register. This second write does the same plus it enables the capture.

7. Read the PTP_ESTS register for bit 0 set. If not, wait and repeat step 6. Once bit 0 of PTP_ESTS has been set, determine the event timestamp length (1-4 16-bit words) by adding 1 to bits 7:6 of the PTP_ESTS value. Ensure the Event number is 7, (the PTP_ESTS value bits 4:2 equal 7). Ensure the event was a rising edge. This is indicated by the value of PTP_ESTS bit 5 equaling 1.

8. Read the PTP_EDATA register. The event timestamp is returned as follows: 

• Event nanoseconds bits 15:0
• Event nanoseconds bits 29:16
• Event seconds bits 15:0
• Event seconds bits 31:16

9. Subtract (3 times the reference clock period + 11) from the timestamp; with the typical 8 ns reference clock period, this value is 35 ns. This corrects for the pin input delay and edge detection.

10. Calculate the phase error as (100 – (event timestamp mod 100)). If the result is equal to the clock period (100 ns in this case), the phase error is 0. If the phase error is within 10 ns of the clock period (91 – 99 ns in this case), set a flag “HighValue”. This is equivalent to a negative phase error of between -9 and -1 ns.

11. Average the phase error. If there are small positive and negative phase error samples, HighValue is set and a phase error sample is less than 10 ns, the clock period must be added to the sample in order for it to be averaged correctly:

•  If (HighValue & error[sample]<10) error[sample] += clkout_period

12. If the average phase error is greater than the clock period, subtract the clock period to get the final average phase error.

13. Calculate the correction value, which is the average phase error plus twice the reference clock period:

• Correction = 2 * ref_period + avg_phase_error

14. . Do a step adjustment to the 1588 clock time:

• Write the correction value to PTP_TDR.
• Write PTP_STEP_CLK (0x8) to PTP_CTL.

Is this procedure aligned with what you have already tried?

Thank you,

Nikhil 

Dear Nikhil, 

Thank you so much for the detailed steps. Yes, that is the procedure I tried, but nothing happened. I have a couple of follow-up questions. 

1. In step 3, we set one board to RMII master mode, another to slave mode. Reference clock in RMII Master Mode is 50 MHz and in Slave mode it is 25 MHz. In this case, do we need to set both the clk_out as 10 MHz or one as 20 MHz, another as 10 MHz.

2.In step 5, how can we take 100 samples of the CLK_OUT phase error? It is not clear to me. In addition, it looks like step 6 to step 10 is the description of how to get one phase error. What is the relation between step 5 and the later steps. 

3. in step 10, how do I set a flag "HIghValue"?

Thanks for the help again!

Regards,

Cheng

Hi Cheng,

To answer your questions:

1. Both should be set to 10 MHz.

2. As you mentioned, steps 5-10 measure 1 sample of the CLK_OUT phase error. Else,100 samples of CLK_OUT phase error can be measured with oscilloscope, but tracking individual samples may be tough. Please measure avg. value. Steps 6 to 10 are should be subpoints of step 5. These steps are equivalent to step 3 in the example of section 3.2 in AN-1729. 100 samples is a recommendation to provide an accurate average value reading of phase error.

3. "HighValue" is a Boolian variable placeholder. If there is a phase error sample within 10ns of the clock period, set "HighValue" to 1 when using the equation in step 11. This is used in the calculations and is not a flag raised by the PHY. To break this equation down further, if there was a sample with a phaser error within 10ns of the clock period, the clock period must be added to this sample for an accurate averaging measurement:

• IF(HighValue & (error[sample]<10ns)
  • error[sample]+= clock_period

Additionally, an extra step may be used for loading the PTP_TDR clock correction. Please try adding PTP_LOAD_CLK after you set PTP_TDR and before you set PTP_STEP_CLK in step 14.

I hope this clears up your questions. Please let me know if this helps, or if you have any further questions. 

Thank you,

Nikhil

Hi Nikhil, 

Unfortunately, I was not able to realize the phase alignment. The Enable Synchronous Ethernet allows me to have a relative clock alignment but with phase difference. BTW I don't think  Enable Synchronous Ethernet is mentioned in the procedure in AN-1729. Why do I need to enable this function? 

The equation in the procedure as you also showed above seems to me that phase alignment should be real-time compensation instead of just inputting a number through register. The video I posted previously (Time Sync Demo), for example, clearly showed a real-time adjustment. Is there supposed to be coding involved here? 

Regards,

Cheng

Hi Cheng,

We are looking into this issue and will provide feedback by Wednesday next week.

Thank you,

Nikhil

Hi Cheng,

This may require the gptp driver running on host. See link below for software details from previous thread:

The Software Development Guide (SDG) and the EPL C code reference library will be good references for our IEEE 1588 implementation. The SDG and the EPL are available on the web at:

www.ti.com/.../snlc036

The EPL C code reference library includes functions that should help you understand the device functionality and should help in developing a driver.

Thank you,

Nikhil