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Original question:

TPS65981: Legacy usb protocol switching

TPS65981: External N-FET Gate Drive Is Too Low

Andy Goulbourne
Prodigy 245 points
Part Number: TPS65981

4721.D1987_2_USB_PD_ONLY.pdfPS65981 with 2 x External N-FETS for a very low RDSon power path and as a power sink.    See attached redacted schematic

Using 5 / 9 / 15V voltages.  

We are seeing that the gate drive (X93) is only 2V above the source so the FET is not switched on and only the body diode is conducting. 

X92 is 5.5V above the source and fully on.  

Can you please think of any reason why the gate drive on X92 is so low pleae.

The datasheet shows that the gate drive (VGSEXT) should be between 4.5 and 7.5V

Thanks

  • 0
    Prodigy 245 points

    Please stand down, on this,  I think the problem may not be with the TI chip, but with the external FET.

  • 0 in reply to Andy Goulbourne
    TI__Genius 12700 points

    Hi Andy,

    No problem, if you'd like, you can check out how the external power path is configured on the EVM User's Guide and compare with your design.

    Thank you,

    Hari

  • 0 in reply to Hari Patel1
    Prodigy 245 points

    Hi,  I have checked against our actual TPS65981 evaluation card and it behaves in the exactly the same was our design.

    To clarify

    on light loads of

    300mA, the Vgs voltage on HV_GATE2 is 2.3V (the data sheet (VGSEXT minimum is 4.5V)

    750mA -> Vgs = 2.77V

    1A -> Vgs = 3.71V

    1.3A  -> Vgs = 5.8V

    The issue we have is that out current rises rapidly and the TS65981 can't track the rising current with a rising gate voltage quickly enough.  We'd expect VGSEXT to be a minimum of 4.5V all the time.

    Is there any way this is a firmware issue of is there an errata in the datasheet on VGSEXT that we are not aware off?

  • 0 in reply to Andy Goulbourne
    TI__Genius 12700 points

    Hi Andy,

    Do you have any scope captures showing this behavior and PD logs that I could look at? 

    What is the VBUS that you negotiate a contract at and what device are you connecting on the USB Type-C port?

    Thank you,

    Hari

  • 0 in reply to Hari Patel1
    Prodigy 245 points

    Hi Hari

    See attached, the blue trace is the current step of 0.2A per graticule , so 0.3A board quiescent (not shown) plus the measured step.

    The VBUS is negotiated at 9V, we are using an Anker USB PD power brick as a power source.  Down stream is our own custom mircoprocessor,  its is configured to not boot during these tests and the step is from an electronic load.  

    The yellow trace is the gate signal to the FET, measured from X93 on our design. 

    As can be seen,

    With a 0.3-1.1A step the gate rises from 11.3V to 14V but quite slowly. 

    With a 0.3-2.1A step the gate rises from 11.3V to 14.8V and is much quicker.

    Andy

  • 0 in reply to Andy Goulbourne
    TI__Genius 12700 points

    Hi Andy,

    Per the PD Specification document, to be compliant, you should also not be pulling any current when transitioning to a different PDO. I think this could be causing the issue you may be seeing with the external NFET, especially if you are trying to pull 2A or so during that transition. I would recommend taking a look at the PD specification to make sure you are being compliant when testing.

    Here's a diagram from the specification document showing the transition: 

    Thank you,

    Hari