The way I understand it, the PCI System part of the XIO2001 has pins that are setup as either Input or Output.
When setup as Output, they can be driven High or Low.
From the "Bus Parking" Section of SCPA045D,
these signals are the address/data lines, the command/byte enables, and a valid parity.
1. The DS says the I/O cell design is a 3-state bi-directional buffer - this means High/Low/Hi-Z?
2. How can the I/O cell output be set to Hi-Z during power up? (see below for details)
So, if VDD_33 is applied before VDD_15 - there is a possibility a pin could be setup as an Output and driven H/L. (default state)
But the designer might need that pin to be an Input. In this case, if VDD_33 is applied before VDD_15, maybe the XIO2001 drives a pin L, while the other device on the bus tries to drive that pin H. This results in a short.
Does 1.5V need to be applied first to keep these PCI pins from being driven before "setup" is completed? (deciding which pins are Input or Output)
If so, what kind of timing requirements are there between 1.5V ➡ 3.3V power sequence, to make sure the pins aren't driven until they are all properly configured as an input or output? How long do you have to wait after powering VDD_15 to be sure all IOs are configured correctly as Input or Output...?
