Hello
Now we are testing eye diagram at CMLout pin for Des90UB954. Our set up is connect camera(953) to Des90UB954 via a coax cable. Then use the oscilloscope to test the eye diagram at the CMLout pin .
We set clock recovery : PLL-customer/ type I /Loop bandwidth 10MHz according to the 6.6 chapter Ac electric input jitter test frequency in Des954 datasheet. (Because we use CSI-2 mode , the CSI-2 clock frequency is 700Mhz , so Fpdlink_PCLK is 700/4=175MHz, loop BW=175/15=11MHz).
Then we get the eye diagram , we found there is only eye width requirement in table 16 /figure17, 0.45 UI , no eye height requirement. We can not judge if we can pass the test.
So I try to found if there are other requirement for the eye diagram in the 954 ds. So I find that there is input jitter requirement, max value is 0.4UI, not sure if we can use the requirement as the judge standard of eye diagram at CMLout pin. If we can use that as the requirement , does that mean this is jitter is at ber=10^(-12) condition?
And for eye height, if we can use 953 eye height 425mV Vp-p (953 ds) as judge standard?
Thanks!
