DP83867IR: Review Schematics Gigabit ethernet(RGMII) using DP83867IRRGZT.

Hi Inho,

I am in the process of reviewing your schematic and will get back to you tomorrow with comments.

Regards,

Adrian Kam

Hi Inho,

Below are the comments/questions I have regarding your schematic:

1. For VDDIO, it should be a 3.3V supply. 3V is too small.
2. If VDDIO is 3.3V, then the oscillator should use the same voltage instead of 1.8V. For 3.3V, a capacitor divider is needed, as shown in the image below. CD1 and CD2 should be 27 pF. Also, may I ask what the 33 ohm resistor at the OUT pin of the oscillator is for?
3. I recommend changing the capacitor connecting ground to chassis ground to 4700 pF and adding a 1 Mohm resistor in parallel with the capacitor.
4. Looking at the RJ45 Jack, it seems the center taps on the side with capacitors are all shorted and connected to VCC pin. If there is something connected to the VCC pin, like in your schematic, then it could cause problems. I suggest either leaving the VCC pin unconnected, or finding a new part that does not have those center taps shorted.
5. Make sure the 0.1uF and 1uF capacitors for VDDA2P5 are close to the device.

Regards,

Adrian Kam

Attempt to reupload capacitor divider diagram

Dear Adrian,

Below this reply for your comment. 

1. 3V is 3.296Vdc. Is that good?

2. I designed that circuits refer to ADI reference EV-KIT of schematics.(Below refer to linked website page 15 of 28). That EV-kit is working good.

www.analog.com/.../ADSP-SC589_EZ-Board_Schematic-Rel_2-0B.pdf

3. I attach "Add R.PNG". Is that right?

4. You mean not connect VCC of that RJ45. is that right?
And, I have additional question : Is that RJ45 connector need ESD
suppressor if not connected VCC of that part ?

5. Ok. I see.

Thank you.

Best Regards,

Inho Jeon

Dear Adrian,

In the DataSheet, the XI ranges from -0.3 to 2.1V.

If so, the OSC with 1.8V power supply can be directly connected to XI without Cap, isn't it?

And, the 33 ohm series resistance of XI is for damping purposes.

Thank you.

Best regards,

Inho Jeon

Hi there,

Adrian is currently out of the office.  Please expect some delay in answers in the upcoming days during this holiday. 

Thanks!

Hi Inho,

See below for my responses:

1. According to the recommended operating conditions section of the datasheet, 3.296VDC should be good.
2. If 1.8V power supply is used for the oscillator, then the capacitor divider is not needed. However, we recommend that the power supply's voltage for the oscillator match the VDDIO voltage that you are using. In your case, since VDDIO is 3.3V, then the clock source should also be 3.3V as shown in the diagram I uploaded in an earlier reply. Since a 3.3V power supply is being used for the oscillator, then the capacitor divider is needed.
3. That is correct.
4. Yes, that is correct. Also, an ESD suppressor should not be necessary.

Regards,

Adrian Kam

Dear Adrian,
Thank you for reply.

I want to use 1.8V power for oscillator to save parts.
Is that designed circuits have working problems?
If it is, please inform me specifically.

And, I want to know why it could cause problems when connected to the VCC of RJ45 connector.(That part is I attached before)

Also,I want to know why not need to ESD suppressor for that RJ45 connector.

Thank you.

Best regards,

Inho Jeon

Hi Inho,

After discussing with my team more, allow me to correct some of my mistakes in my replies:

1. Using 1.8V power for oscillator is fine and should not cause any problems. Since you are using 1.8V, the capacitor divider is not necessary.
2. If your application requires it, you can keep the external ESD suppressors. It should not cause any issues, just make sure the VCC pin of the RJ45 connector is left floating. I previously missed where the "VDD_TI_ETH" net came from and thought it was only connected to the VCC pin and the ESD suppressors.

We have had issues in the past where not leaving the center tap floating causes some marginal IEEE compliance failures. As a result, we recommend leaving the VCC pin floating.

Regards,

Adrian Kam

Dear Adrian,
Thank you for your reply.

I don't understand your reply No. 2.
So, Reply for below my questions,please.

You mean that VCC port of RJ45 Jack is not need to connected "VDD_TI_ETH", Is it right?
And, You mean that VDD port of ESD suppressor(D35,D20: I attach that part datasheet) is need to connected "VDD_TI_ETH", Is it right?

Best Regars,
Inho Jeon

824001(TVS_Diode_Dante_LAN_ESD).pdf

Hi Inho,

You are correct.

The VCC port of RJ45 should not be connected to "VDD_TI_ETH" or any other net. It should be left floating.

The VDD port of ESD suppressor should be connected to "VDD_TI_ETH".

Regards,

Adrian Kam

Dear Adrian,
Thank you for reply.

On datasheet, Supply Configuration is 2 ways.
But I don't understand about that.
So, please Inform me about "Two Supply Configuration" & "Three Supply Configuration specifically".

And, I want to know function of "VDDA1P8".

Thank you.
Best Regards,
Inho Jeon

Hi Inho,

For the DP83867, the "Two Supply Configuration" uses 1.1V and 2.5V supplies, while the "Three Supply Configuration" uses 1.1V, 1.8V, and 2.5V supplies. 

The three supply configuration has an overall lower power consumption compared to the two supply configuration. Below is the link to an app note with power consumption data for the DP83867.

https://www.ti.com/lit/an/snla241/snla241.pdf?ts=1609955756478

For two supply, VDDA1P8 is left floating, but for three supply, an external 1.8V analog supply is connected to VDDA1P8.

If you have any other questions, please start another thread, as this thread has been resolved.

Regards,

Adrian Kam

Dear Adrian,

Thank you for reply.
I checked difference of current consumption for 2.5V on 2 supply ways.

And, Is it available comment & review for PCB artwork file?

Thank you.
Best Regards,
Inho Jeon

Hi Inho,

If you are referring to the PCB layout, then I can review that as well if you put the files in a reply.

Regards,

Adrian Kam

Dear Adrian,

I attach PCB & schematics files.(PCB file is designed with PADS LAYOUT) 

Please, Review & Comment.

Thank you.
Best Regards,
Inho Jeon

4643.TI_ETH_SCH.zip

Hi Inho,

I am in the process of reviewing the layout and will get back to you by EOD Friday at the latest.

Regards,

Adrian Kam

Hi Inho,

Below are my comments/recommendations on your layout:

1. If possible, place the RBIAS resistor closer to the PHY
2. The total length of the MDI traces should be less than 2 inches. Also, ensure a controlled differential impedance of 100 ohms.
3. The MII traces are less than 6 inches, which is good. Keep trace length matching to within 50 mils if you are using 1G speed, or 100 mils if you are only using 100M speed.
4. Ensure the MII traces have a controlled single ended impedance of 50 ohms.
5. MII traces should not cross unless properly separated by a GND layer. It seems to cross with signals on layer 5 without a GND layer in between.
6. Length matching should be done on the mismatched end. That does not seem to be the case for all the MII traces.
7. For the MII and MDI traces, try to minimize the amount of vias used.
8. Recommend using power planes to avoid IR drops from supply to pin. Use vias if stitching power planes across layers.
9. Chassis/Earth GND should be a separate plane and be isolated from the rest of the board by at least 20 mil on all layers.

It is possible that some of these recommendations may have already been done, but my layout editor did not properly import everything.

Regards,

Adrian Kam

Dear Adrian,

Thank you for reply.

Below this, I comments your answers for my PCB.

Please, reply for my comments. 

1. If possible, place the RBIAS resistor closer to the PHY => OK, I'll replacement that part.
2. The total length of the MDI traces should be less than 2 inches. Also, ensure a controlled differential impedance of 100 ohms. => It is applied impedance matched PCB stacks by line width.
3. The MII traces are less than 6 inches, which is good. Keep trace length matching to within 50 mils if you are using 1G speed, or 100 mils if you are only using 100M speed. => OK. It is applied.
4. Ensure the MII traces have a controlled single ended impedance of 50 ohms. => It is applied impedance matched PCB stacks by line width.
5. MII traces should not cross unless properly separated by a GND layer. It seems to cross with signals on layer 5 without a GND layer in between.=> Is that must to apply for my PCB? Your comment is hard to applied my PCB. Because so many signal lines in my PCB.
6. Length matching should be done on the mismatched end. That does not seem to be the case for all the MII traces. =>OK, thanks.
7. For the MII and MDI traces, try to minimize the amount of vias used. => Ok, I try to minimize number of VIAs.
8. Recommend using power planes to avoid IR drops from supply to pin. Use vias if stitching power planes across layers. => Ok, I add more VIAs for power planes.
9. Chassis/Earth GND should be a separate plane and be isolated from the rest of the board by at least 20 mil on all layers.=> OK, I'l modified Chassis/Earth GND planes.

And, on your comment, MII is  RX_CTRL,RX_D3, RX_D2, RX_D1, RX_D0, RX_CLK / TX_CTRL, GTX_CLK, TX_D0, TX_D1, TX_D2, TX_D3, right ? 

Thank you.

Best Regards,

Inho Jeon

Dear Adrian,
Thank you for reply.

5-Layer of signals(that is acrossed MII traces of DP83867IRRGZT) is not high-speed signals. it is just logic signals for ON/OFF[3v/0v] conditions of peripheral devices.

So, I think it is not affect MII traces of DP83867IRRGZT.

How about your opinions?

Thank you.
Best Regards,
Inho Jeon

Hi Inho,

In that case, I agree with you in that it probably will not affect the MII traces. Also, looking closer, the traces seem to be mostly perpendicular to each other, which should reduce crosstalk further.

Regards,

Adrian Kam