TDP158: EDID with TDP158

Joe

The TDP158 is a redriver, it does not have stored EDID data. If the FPGA is the sink, then the EDID needs to be stored in the FPGA.

Is the camera output a DC-coupled HDMI or AC-coupled HDMI? 

Thanks

David

Hi David,

I am interfacing with an SDI camera and using the LMH1297RTVT and using an SDI Receiver IP on the FPGA. Is there a web site where I can find the EDID data, some kind of software that can generate this EDID data? 3065872. How do I read the monitor's EDID parameters?

Thank you

Joe

Joe

Are you trying to interface a FPGA HDMI Transmitter and a HDMI monitor? I am sorry that I thought you are trying to interface the camera and FPGA through the HDMI interface.

If you are trying to interface a FPGA HDMI transmitter and a HDMI monitor, the EDID information is already present inside the monitor. The FPGA has to use the DDC bus to read the EDID from the monitor. Different monitors will have different EDID to reflect the difference in the manufacturer, resolution, etc. The DDC bus uses the same protocol as the I2C bus. So the FPGA needs to implement the DDC primary function in order to read the EDID from the monitors.

Thanks

David 

David,

HI, I have been looking a Zynq Ultrascale+ MPSOC Dev Kit that has HDMI TX and they are using the SN65DP159 ReTimer. Like I said, I'm a newbie here and without your comments and looking at Dev Kits I'm lost. Which device is most practical in what I am doing? Could I make things easy by only supporting 1920x1080p at 60Hz resolution and timing? Is the DDC bus on the ReTimer or ReDriver?

Thank you

Joe

Joe

Would you please accept my friendship request and maybe we can have a call to go over your questions?

Thanks

David

Hi David. I accepted the request.

Joe

David,

HI, I the SN65DP159 the SCL_SRC and SDA_SRC I believe is the inteface where the DDC bus can be read.

Joe

Joe

The TDP158 can either snoop the DDC bus (no 5V to .3.3V level shifting) or provide the 5V to 3.3V level shifter function between the source and the sink DDC bus. 

When the TDP158 provides level shifting function, the FPGA issues a DDC read request to the TDP158 SDA_SRC and SCL_SRC at 3.3V, the TDP158 then level shifts the read request to 5V and sends the request to the sink. When the sink returns with the requested data, the TDP158 again pass the requested data from the sink to the source.

Thanks

David   

David,

Hello, here is what I have so far.

VIB 21.pdf

Joe,

On the schematic

1. Since you are using the TPD12S016, you may want to remove the TPD4E05U06QDQARQ1 ESD protection on the main link and use the TPD12S016 on the main link.

2. Please add HDMI common mode choke on the output

3. You can remove the EEPROM on the CTL_SDA and CTL_SCL and use the FPGA I2C primary to control the DP158/159

Thanks

David

David,

Hello, quick question for you about output chokes. I was looking at the EVM for the DP159 they use chokes on the output diff pairs but on the EVM for the DP158 I don't see any chokes. Do you recommend chokes with the DP158?

Thank you

Joe

Thanks again!

Hello, are you suggesting the following:

I found this at:

Now, I'm searching for a common mode choke part number. Can you recommend a part#?

Thank you

Joe

Joe

For ESD, I would recommend the TPD4E02B04. This one has a lower line capacitance than the ESD224 (0.25pF vs. 0.5pF),

For common mode choke, you can refer to the Murata website, 

Murata selection guide

We used Murata DLW21SN900HQ2L on our EVM.

Thanks

David

Hello,

Thank you for the information. Can you please send me a link to the EVM that used the Murata part.

Thank you

Joe

Joe

Please see this link, 

Common mode choke portion of the schematic is on page 15.

Thanks
David 

HI David,

Thanks for the page number of the chokes. Says it there a separate set of schematics that is only schematics? Little easier to read.

Thank you

Joe

Wonderful!

Thank you very much,

Joe