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Original question:

HD3SS3220: Absolute maximum ratings of DIR pin

HD3SS3220: DIR pin VCC33 pull-up referred to VDD5 power on requirements

Fabio Garzetti
Prodigy 30 points
Part Number: HD3SS3220

Hello,

I'm designing a scheme for a USB-C UFP using HD3SS3220. My question is regarding the pull-up voltage of DIR pin.

It is clear that the DIR ping should pulled-up with 3.3V (see this answer), but it is also true that this voltage should be applied after VDD5 rail (see 7.3.12 VDD5 and VCC33 Power-On Requirements on ti datasheet) because it is a non-failsafe pin. I'm designing a scheme like ti suggested in the datasheet "8.2.4 Typical Application, UFP Port", and in the table 8-3 there is this statement: for VDD5 VBUS from Type-C port can be used. How is it possible? The VBUS and therefore the VDD5 can be disconnected and reconnected without any respect of VCC33 and therefore a violation of power timing for DIR pin.

Thanks in advance,

Fabio

  • 0
    TI__Guru 64326 points

    Hi Fabio,

    Typically systems that power from Vbus will use LDO or other regulator to generate 3.3V rail. If these are separate, system must be aware of Vbus disconnect to disconnect 3.3V supply.    

  • 0 in reply to Malik Barton57
    Prodigy 30 points

    Hello Malik,

    Thanks for the answer.

    The first idea was to use an external 3.3V supply but now I'm taking into consideration to use an LDO to generate the 3.3V (only for HD3SS3220) directly from VBUS as you suggested. In this case, using a LDO, I will not respect the t_VDD5V_PG timing requirement (Figure 7-2 of the datasheet), is this ok? 

    As a side note, I think you should review this phrase (see below) in the datasheet (Pag. 17) because there is not possible to pull-up the DIR pin to a rail different from VDD5 (https://e2e.ti.com/support/interface/f/138/t/827863

    The HD3SS3220 non-failsafe pins are the following: PORT, ADDR, SDA/OUT1, SCL/OUT2, INT_IN/OUT3,
    VCONN_FAULT_N, and DIR. If any of these non-failsafe pins are pulled-up to a supply other than VDD5, then
    VDD5 supply must be powered up before the VCC33 supply as depicted in Figure 7-2. If it is not possible to
    power up VDD5 before VCC33, then the ENn_CC pin must be held high while both supplies are ramping and
    then asserted low after both supplies are stable as depicted in Figure 7-3.

    Best,

    Fabio

  • 0 in reply to Fabio Garzetti
    TI__Guru 64326 points

    Hi Fabio,

    This timing should still be followed to ensure a proper reset. In this case a LDO with a EN pin should be used. Adding an RC circuit, sourced from Vbus, to delay the ramp of 3.3V rail at least 2 ms after 5V is stable should allow the design to meet all the necessary constraints.

    We are working internally to add some clarification for this comment. 

  • 0 in reply to Malik Barton57
    Prodigy 30 points

    Hi Malik,

    Thank you very much for all your clarifications.

    Best,

    Fabio

  • 0 in reply to Fabio Garzetti
    TI__Guru 64326 points

    Hi Fabio,

    Happy to help. Also please keep in mind the above solution works assuming the EN pin of the LDO is active high.