SN65DSI86: BPP conversion questions

Hi Kailyn,

2、  Qualcomm输出RGB888 + Bridge IC  output 888 + RGB666 LCD，LCD could appear；

So it looks like 24bpp to 18bpp is working correctly, why do they say the conversion would fail?

What resolution are they trying to send?

For the 18bpp packet, is this loosely packed or tightly packed DSI packet?

Thanks

David

Hello David,

Thank you for your reply.

From the configuration of the configure 1&2,  we could find that if the input and output of DSI86 are consistent(for example configuration2: the input and output are both RGB888 of DSI86, even if the LCD is RGB666), the LCD could also  appear. 

I would ask the customer to send me the image of the LCD and confirm the packet is  loosely or tightly.

Best regards

Kailyn 

Hello David，

I have confirmed with the customer, the RGB666 18bit is loosely packet. The LCD resolution is 1920*1080.

Below is the normal image and NG image.

Hi Kailyn

The SN65DSI86 transmits either 18bpp or 24bpp over the DisplayPort interface based on the DP_18BPP_EN bit. When this bit is cleared and 18 bpp is being received on DSI interface, the SN65DSI86 performs the following translation of the 18 bpp into 24 bpp: new[7:0] = {original[5:0], original[5:4]}. When the DP_18BPP_EN bit is set and 24 bpp is being received on DSI interface, the SN65DSI86 performs the following translation of 24 bpp to 18 bpp: new[5:0] = original[7:2]. Are they setting this bit?

Can you please dump out the DSI86 registers in both the good and bad case?

Thanks

David

Hi David,

Yes, he has set the DP_18BPP_EN bit, the difference configuration of the OK image and NG image is the DP_18BPP_EN bit. Is there any other configuration else except DP_18BPP_EN? 

Best regards

Kailyn 

Kailyn 

The DP_18BPP_EN bit is the only bit needs to be set to convert between the 18bpp and 24bpp. But you also need to make sure the DSI86 output matches with the panel's requirement. For example, if the panel requires RGB888, then the DSI86 needs to output RGB888 as well.

Thanks

David

Hi David,

Yes, what you said is the configuration 3&5(DSI output matches LCD panel)  as the customer said, and the differences configuration of the OK image and NG image is the DP_18BPP_EN setting.  Is there any other else to pay attention to?

 1. Qualcomm output RGB888 + Bridge IC SN65DSI86 output 888 + RGB888 LCD，LCD could appear；

2、  Qualcomm output RGB888 + Bridge IC  output 888 + RGB666 LCD，LCD could appear；

3、  Qualcomm output RGB888 + Bridge IC output 666 + RGB666 LCD，NG；

4、  Qualcomm output RGB888 + Bridge IC output 666 + RGB888 LCD，NG；

5、  Qualcomm output RGB666 + Bridge IC output 666 + RGB666 LCD，NG；

Best regards

Kailyn 

Kailyn

Are these the same panels with the same EDID? Different EDID would require different DSI86 video registers programming value.

Again, I am confused with your statement that NG image is the DP_18DPP_EN setting. The 2. Qualcomm output RGB888 + Bridge IC  output 888 + RGB666 LCD，LCD could appear, Is this with the DP_18DPP_EN bit being set to convert from the DSI 24 bit to DP 18 bit? When the DP_18DPP_EN bit is set, then 18BPP format will be transmitted over eDP interface regardless of the DSI pixel stream data type format.  

For all cases, can you please dump out the DSI86 registers, particular registers 0xF0 to 0xF8?

Thanks

David

Hi David，

reg: 0xa, val: 0x85
reg: 0xb, val: 0x0
reg: 0xc, val: 0x0
reg: 0xd, val: 0x1
reg: 0xe, val: 0x0
reg: 0xf, val: 0x0
reg: 0x10, val: 0x26
reg: 0x11, val: 0x0
reg: 0x12, val: 0x53
reg: 0x13, val: 0x53
reg: 0x14, val: 0x0
reg: 0x15, val: 0x0
reg: 0x16, val: 0x0
reg: 0x17, val: 0x0
reg: 0x18, val: 0x0
reg: 0x19, val: 0x0
reg: 0x1a, val: 0x0
reg: 0x1b, val: 0x0
reg: 0x1c, val: 0x0
reg: 0x1d, val: 0x0
reg: 0x1e, val: 0x0
reg: 0x1f, val: 0x0
reg: 0x20, val: 0x80
reg: 0x21, val: 0x7
reg: 0x22, val: 0x0
reg: 0x23, val: 0x0
reg: 0x24, val: 0x38
reg: 0x25, val: 0x4
reg: 0x26, val: 0x0
reg: 0x27, val: 0x0
reg: 0x28, val: 0x0
reg: 0x29, val: 0x0
reg: 0x2a, val: 0x0
reg: 0x2b, val: 0x0
reg: 0x2c, val: 0x20
reg: 0x2d, val: 0x80
reg: 0x2e, val: 0x0
reg: 0x2f, val: 0x0
reg: 0x30, val: 0xe
reg: 0x31, val: 0x80
reg: 0x32, val: 0x0
reg: 0x33, val: 0x0
reg: 0x34, val: 0x98
reg: 0x35, val: 0x0
reg: 0x36, val: 0x13
reg: 0x37, val: 0x0
reg: 0x38, val: 0x10
reg: 0x39, val: 0x0
reg: 0x3a, val: 0x3
reg: 0x3b, val: 0x0
reg: 0x3c, val: 0x0
reg: 0x3d, val: 0x0
reg: 0x3e, val: 0x0
reg: 0x3f, val: 0x0
reg: 0x40, val: 0x3c
reg: 0x41, val: 0x42
reg: 0x42, val: 0x0
reg: 0x43, val: 0x0
reg: 0x44, val: 0x80
reg: 0x45, val: 0x0
reg: 0x46, val: 0x48
reg: 0x47, val: 0x8
reg: 0x48, val: 0x5c
reg: 0x49, val: 0x4
reg: 0x4a, val: 0xb8
reg: 0x4b, val: 0x0
reg: 0x4c, val: 0x21
reg: 0x4d, val: 0x0
reg: 0x4e, val: 0x20
reg: 0x4f, val: 0x80
reg: 0x50, val: 0xe
reg: 0x51, val: 0x80
reg: 0x52, val: 0x80
reg: 0x53, val: 0x7
reg: 0x54, val: 0x38
reg: 0x55, val: 0x4
reg: 0x56, val: 0x0
reg: 0x57, val: 0x0
reg: 0x58, val: 0x40
reg: 0x59, val: 0xe4
reg: 0x5a, val: 0x9
reg: 0x5b, val: 0x3
reg: 0x5c, val: 0x11
reg: 0x5d, val: 0x0
reg: 0x5e, val: 0x10
reg: 0x5f, val: 0x0
reg: 0x60, val: 0xa0
reg: 0x61, val: 0x60
reg: 0x62, val: 0xa4
reg: 0x63, val: 0x0
reg: 0x64, val: 0x0
reg: 0x65, val: 0x1
reg: 0x66, val: 0x0
reg: 0x67, val: 0x0
reg: 0x68, val: 0x0
reg: 0x69, val: 0x0
reg: 0x6a, val: 0x0
reg: 0x6b, val: 0x0
reg: 0x6c, val: 0x0
reg: 0x6d, val: 0x0
reg: 0x6e, val: 0x0
reg: 0x6f, val: 0x0
reg: 0x70, val: 0x0
reg: 0x71, val: 0x0
reg: 0x72, val: 0x0
reg: 0x73, val: 0x0
reg: 0x74, val: 0x0
reg: 0x75, val: 0x1
reg: 0x76, val: 0x2
reg: 0x77, val: 0x1
reg: 0x78, val: 0x80
reg: 0x79, val: 0x81
reg: 0x7a, val: 0x0
reg: 0x7b, val: 0x0
reg: 0x7c, val: 0x0
reg: 0x7d, val: 0x0
reg: 0x7e, val: 0x0
reg: 0x7f, val: 0x0
reg: 0x80, val: 0x0
reg: 0x81, val: 0x0
reg: 0x82, val: 0x0
reg: 0x83, val: 0x0
reg: 0x84, val: 0x0
reg: 0x85, val: 0x0
reg: 0x86, val: 0x0
reg: 0x87, val: 0x0
reg: 0x88, val: 0x0
reg: 0x89, val: 0x1f
reg: 0x8a, val: 0x7c
reg: 0x8b, val: 0xf0
reg: 0x8c, val: 0xc1
reg: 0x8d, val: 0x7
reg: 0x8e, val: 0x1f
reg: 0x8f, val: 0x7c
reg: 0x90, val: 0xf0
reg: 0x91, val: 0xc1
reg: 0x92, val: 0x7
reg: 0x93, val: 0x24
reg: 0x94, val: 0x81
reg: 0x95, val: 0x0
reg: 0x96, val: 0x1
reg: 0x97, val: 0x4
reg: 0x98, val: 0x1
reg: 0x99, val: 0x0
reg: 0x9a, val: 0x0
reg: 0x9b, val: 0x0
reg: 0x9c, val: 0x0
reg: 0x9d, val: 0x0
reg: 0x9e, val: 0x0
reg: 0x9f, val: 0x0
reg: 0xa0, val: 0x1
reg: 0xa1, val: 0xff
reg: 0xa2, val: 0xff
reg: 0xa3, val: 0x0
reg: 0xa4, val: 0x0
reg: 0xa5, val: 0x0
reg: 0xa6, val: 0x0
reg: 0xa7, val: 0x0
reg: 0xa8, val: 0x0
reg: 0xa9, val: 0x0
reg: 0xaa, val: 0x0
reg: 0xab, val: 0x0
reg: 0xac, val: 0x0
reg: 0xad, val: 0x0
reg: 0xae, val: 0x0
reg: 0xaf, val: 0x0
reg: 0xb0, val: 0x4
reg: 0xb1, val: 0x78
reg: 0xb2, val: 0xac
reg: 0xb3, val: 0xac
reg: 0xb4, val: 0x8
reg: 0xb5, val: 0x6c
reg: 0xb6, val: 0x9c
reg: 0xb7, val: 0x9c
reg: 0xb8, val: 0xc
reg: 0xb9, val: 0x5c
reg: 0xba, val: 0x5c
reg: 0xbb, val: 0x5c
reg: 0xbc, val: 0xc
reg: 0xbd, val: 0xc
reg: 0xbe, val: 0xc
reg: 0xbf, val: 0xc
reg: 0xc0, val: 0x3f
reg: 0xc1, val: 0x3f
reg: 0xc2, val: 0xf
reg: 0xc3, val: 0x0
reg: 0xc4, val: 0x0
reg: 0xc5, val: 0x0
reg: 0xc6, val: 0x0
reg: 0xc7, val: 0x0
reg: 0xc8, val: 0x0
reg: 0xc9, val: 0x0
reg: 0xca, val: 0x0
reg: 0xcb, val: 0x0
reg: 0xcc, val: 0x0
reg: 0xcd, val: 0x0
reg: 0xce, val: 0x0
reg: 0xcf, val: 0x0
reg: 0xd0, val: 0x0
reg: 0xd1, val: 0x0
reg: 0xd2, val: 0x0
reg: 0xd3, val: 0x0
 

Best regards

Kailyn

Kailyn

Can you please dump out the status registers from 0xF0 to 0xF8 as I don't see them in your thread?

Thanks

David

Hi David，

sn65dsi86: f0: 0
sn65dsi86: f1: 0
sn65dsi86: f2: 0
sn65dsi86: f3: 0
sn65dsi86: f4: 1
sn65dsi86: f5: 0
sn65dsi86: f6: 0
sn65dsi86: f7: 0
sn65dsi86: f8: 1

Best regards

Kailyn

Kailyn

Are they seeing a register difference between the good and the bad case?

Thanks

David

Hi David，

The F0 and F8 are the same between good and bad case.

But other registers are changed randomly.

Could you have any other opinions? 

Best regards

Kailyn