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DP83867IR: DP83867IR: Inquiry about xGMII Error Interrupt

Part Number: DP83867IR

Hi Cecilia,

My thread has locked. so I make new thread.

Here is my thread link.

You requested like below question.

"My question is, are they using the TX_CLK from the MAC? Also have you confirmed that the clocks have the correct skew for TX_CLK and RX_CLK?"

Here is what you requested.

Could you please review and get me feedback?

* TX_CLK is from MAC.

  Their net name is GTX_CLK.

* TX_CLK vs RX_CLK waveform and measured point (40pin - GTX_CLK, 43pin - RX_CLK)

Best Regards,

Michael

  • Hi Cecilia,

    I got an additional inquiry from customer.

    * Inquiry

    When network does not work after booting of system,

    If SW_RESET (BIT15) is forcibly enabled, network is restored normally.

    But, when SW_RESTART (BIT14) is forcibly enabled, network is not restored.

    When I checked description on the data sheet, there is only difference whether register reset or not.

    Could I get information which registers can affect to this issue (network is not work normally)? 

    Could you please review and get me feedback?

    Best Regards,

    Michael

  • Hi Cecelia or Expert,

    Isn't there anyone?

    I'm looking forward to receiving your feedback.

    Pls help.

    Best Regards,

    Michael

  • Hello Michael,

    Regarding reset :

    x1F[15] : Is a hard reset. It clears all registers and internal states of PHY to default state + restarts the link-up sequence.

    x1F[14] : Is a soft reset. It only restarts the link-up sequence.

    Regarding xGMII debug :

    I see a trail of information exchange here. It will be more effective if you can share the information/status over email with me. I will help me to getting attention of more team members to debug this.

    --

    Regards,

    Vikram