• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 2 answers
  • Subscribers 34 subscribers
  • Views 435 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UH947-Q1: dual LVDS input

Tommy Tzeng
Mastermind 6070 points

Part Number: DS90UH947-Q1

Hi Sir,

may we know that DS90UH947-Q1 can support input dual LVDS? because this feature is mention in datasheet.

but the DS90UH947-Q1 receiver has only one set of CLK, we have two sets of CLK from processor.

how to connect or design? is there referene design guide? or schematic? for our reference.

  • 0
    TI__Guru** 113140 points

    Hello Tommy,

    what is mentioned in the datasheet is Single pixle openLDI (D[3:0]) or Dual pixel openLDI (D[7:0]). So these are not dual seperated ports, but one port supporting the dual pixel mode (odd and even) to support higher PCLK and higher bandwidth.

    Please refer to figure 13 and 14 in the d/s.

  • 0 in reply to Hamzeh Jaradat
    Genius 4990 points

    Hello Hamzeh:

    Customer is using dual pixel openLDI and the video resolution is 1920 * 720.

    The front-end video processing chip outputs 8 LVDS data  + 2 clock  (D0-D3, CLK1, D0-D3, CLK2).

    We let processing chip CLK1 connect to pin58 and pin57 of DS90UH947-Q1.

    Please help us to check the schematic and provide recommendations for us.

    Thanks a lot.

    This sentence means "LVDS1 CLK or LVDS2 CLK come from CPU side"

    FPDLINK_DS90UH947.pdf

  • 0 in reply to Statham Su
    TI__Guru** 113140 points

    Hello Statham,

    I will review and get back to you within two days.

  • 0 in reply to Hamzeh Jaradat
    TI__Guru** 113140 points

    Here is my review feedback:

    - Each LVDS pair requires a 100ohm differential termination

    - You need to avoid creating stubs on DOUT traces, by placing the termination resistors place holders directly on the traces.

    - Make sure you have 4.7Kohm pull-up resistors on I2C pins.

    - MODE_SEL0 and MODE_SEL1 they have wrong voltage divider values. Please refer to Table 7 and 8 in the d/s.

    - REM_INTB does not require pull-up resistor.

    - Make sure VDDxx pins Ferrite beads shall have RDC<0.3ohm, and 1Kohm@100MHz. Please refer to figure 35 for the quantity and value of the decoupling caps.