Good afternoon,
IN RGMII layout guidelines, the skew constraint is only mentioned in between data lanes. I believe Clcok signal and control signal needs to be in the same skew requirements.
The CTL signal is used to indicate that a packet is available and if it comes later than the data or earlier than the data there can be some lost in the packet.
Also data lanes are synced to clock so I don't think any skew more than some ps. shall not be allowed in data-clock lane for both TX and RX.
What do you think about this?
Best Regards
