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DS90UB933-Q1: PCLK input jitter tolerance

Yutaka Toyonoh
Prodigy 10 points
Part Number: DS90UB933-Q1

 How much is the actual input jitter tolerance for PCLK using external oscillator mode?

I took a look at the datasheet and found a spec, tJIT1 but it said 1T@NOM only.

It does not make any sense to me. 

How much is the actual PCLK period allowed with that spec?

For example, if PCLK is set to 100MHz, which means the tTCP is 10ns and the tJIT1 NOM is also 10ns.

 

How much are the allowable/expected maximum/minimum PCLK periods?

 

Max ?[ns]

Min ?[ns]

  • 0
    TI__Guru** 103215 points

    Hello,

    In external clock mode, the oscillator clock is used to source the FPD-Link PLL and generate the forward channel serial output. So the jitter on the external clock input is critical to ensure low jitter output on the FPD-Link forward channel. But the PCLK input in this mode is just used to strobe the DIN/HSYNC/VSYNC inputs. It does not directly impact the forward channel jitter. So the main concern is whether or not there is significant enough jitter/skew between the PCLK/data which could result in an incorrect data bit being captured by the parallel receiver. That is why the jitter specification is basically 1UI. 

    Best Regards,

    Casey 

  • 0
    TI__Prodigy 10 points

    Hello,

    Let me clarify.

    Is it 1[UI], not 1T?

    Is it TYPO in datasheet?

    Regards,

  • 0 in reply to Yutaka Toyonoh
    TI__Guru** 103215 points

    Hello Yutaka,

    Sorry I meant 1T in the post above. It is 1T since the interface is not DDR. Data is only strobed on rising or falling edge of the PCLK signal, not both 

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    TI__Prodigy 10 points

    PCLK jitter.pptxHello,

    I'm confused.  Is 1T@NOM spec applied for PCLK input jitter tolerance or clock period?

    Please see attached and answer my query.

  • 0 in reply to Yutaka Toyonoh
    TI__Guru** 103215 points

    Hello Yutaka,

    I will check your PPT and provide a response back by the end of Monday 3/22. Thank you for your patience 

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    TI__Guru** 103215 points

    Hello Yutaka,

    The maximum jitter/skew on the PCLK in this mode is only related to the clock to data sampling relationship. So essentially the PCLK jitter can be up to 1T as long as the clock to data setup and hold time is not violated. Here is an example to show how the clock could move in relation to the data within 1T. You can see that as long as the clock falling edge stays within the DIN bit period and does not violate the setup/hold times tDIS and tDIH, then the DIN bits will be sampled correctly. In this mode, the PCLK jitter does not directly influence the forward channel output jitter since the forward channel is clocked off the external oscillator instead of the PCLK input:

    Best Regards,

    Casey 

  • 0
    TI__Prodigy 10 points

    Hello, Casey,
    Finally, I understood your point.
    Thank you for the support and let's wait the customer feedback regarding the setup/hold time.

    Best regards,