SN65DSI86: What is the maximum resolution of DP output with signal MIPI DSI input port？

user4818118

Prodigy 30 points

Part Number: SN65DSI86

Hi David，

I do some calculate, it seem SN65DSI86 can support 3840 x 2160 30fps, 24bpp via 4-lane MIPI DSI.

Following is my calculation, please help to check about this:

Steam bit rate = 3840 x 2160 x 30 x 24 ≈ 6Gbps

Min_number of DSI lanes = 6Gbp / 2 x 750MHz = 6G / 1.5G = 4

over 4 years ago

0 David (ASIC) Liu over 4 years ago

TI__Guru**** 177071 points

Hi,

The calculation is almost right.

The 3840x2160 is the active horizontal and vertical pixel. To calculate the min_number of DSI lanes, you need the total horizontal and vertical pixel which is

Htotal = Hactive + Hblank

Vtotal = Vactive + Vblank

Assume Hblank = 560 and Vblank = 90

Stream_bit_rate = (3840+560) * (2160+90) * 30 * 24 = 7.128G

So you need all 8 DSI lanes to support 4k@30Hz resolution.

Thanks

David

0 user4818118 over 4 years ago in reply to David (ASIC) Liu

Prodigy 30 points

Thanks David,

If we only have 4-lane MIPI interface, we should chose 18bit bpp to support 4K30, right?

0 David (ASIC) Liu over 4 years ago in reply to user4818118

TI__Guru**** 177071 points

Hi,

Your understanding is correct. In this case, you need to use DSI datatype 0x1E (18-bit RGB-666 packed format).

Thanks

David

Interface

Interface forum

SN65DSI86: What is the maximum resolution of DP output with signal MIPI DSI input port？