• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 32 subscribers
  • Views 669 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN65DSI86: Regarding support of eDP 1.2 version LCD with SN65DSI86

PSG_4
Intellectual 560 points
Part Number: SN65DSI86
Other Parts Discussed in Thread: TEST2

Hi ,

I am planning to use  eDP 1.2  version LCD display (2 lanes of  eDP ) with SN65DSI86 (with only 4 lanes of MIPI DSI input) . Let me know:

1. Is SN65DSI86 can support eDP1.2 version display (2 lanes for data, without  Panel self refresh PSR and without ASSR) ?   

2. The resolution of the display is 1920 x 1200 @ 60 , color is 8 bit  (24bpp) .The maximum pixel clock frequency = 158.73MHz. (2160x 1212x60 ) . Is it possible to stream total  LCD  data through 2 lanes of  eDP interface. 

Regards

PSG_4

  • 0
    TI__Guru*** 140115 points

    Hi PSG_4

    1. DSI86 can support panel without PSR and ASSR. To support panel without ASSR

    The first step to make ASSR_CONTROL read/write is to make sure TEST2 pin is be sampled high at the rising edge of EN pin. It is recommended to pull TEST2 pin to 1.8V thru a 1k to 10k resistor. Once TEST2 is high, the following steps must be performed:

    • Write 0x07 to register 0xFF. This will select Page 7.
    • Write 0x01 to register 0x16. This will make ASSR_CONTROL to be read/write.
    • Write 0x00 to register 0xFF. This will select Page 0.
    • Write 0 to bits 1:0 at register 0x5A. This will change from ASSR to Standard DP.

    2. What is the data rate that can be supported by the panel per lane?

    In order to support the panel stream bit rate, the SN65DSI86 eDP interface must be programmed so that the total eDP data rate is greater than the stream bit rate.

    Stream bit rate = pixel clock * bpp = 158.73 * 24 = 3.80952Gbps

    Assume data rate = 2.7Gbps

    eDP Total Bit Rate = #_of_eDP_Lanes * DataRate * 0.80 = 2 * 2.7 * 0.8 = 4.32Gbps. 

    In this case, 2 lane can be supported.

    Thanks
    David 

  • 0 in reply to David (ASIC) Liu
    Intellectual 560 points

    Hi David, 

    Thanks for reply.

    Again few further queries : 

    1. To support  display  with resolution of  1920 x 1200 @ 60 , color is 8 bit  (24bpp)  and maximum pixel clock frequency = 158.73MHz. (2160x 1212x60 ),  how many  MIPI  DSI channels are required  ? 

    2. Is it  possible to interface  above said display with  4 lane of  MIPI DSI  (Channel A) of SN65DSI86   ?  or   both Channel A and B ( 8  lanes of MIPI DSI)   is required  ? 

    Regards

    PSG_4

  • 0 in reply to PSG_4
    TI__Guru*** 140115 points

    Hi, PSG_4

    Min Required DSI Clock Frequency = StreamBitRate / (Min_Number_DSI_Lanes * 2)

    Assume 4 DSI lanes

    Min Required DSI Clock Frequency = 3.80952 / (4 * 2) = 476.19MHz. 

    DSI86 max supported clock frequency is 750MHz, so you only need to use 4 DSI lanes (Channel A).

    Thanks

    David