DS92LX1621: Jitter measurement

Hirokazu Takahashi

Part Number: DS92LX1621
Other Parts Discussed in Thread: DS92LX1622

Hello Support team,

I want to verify that the input signal jitter on the DS92LX1622 is within the acceptable range (tRJIT: 0.53UI).
The input signal is triggered at point of the rising edge at CLK1, the peak to peak jitter is measured from trigger point to a point after 28 bits.
See attached diagram for details

DS92LX162x jitter (2021 05 06).pptx

I guess the above measurement points will be considered reasonable, because SerDes is one frame at 28 bits and the CDR plays the clock with an end of clock every 28 bits.
Is this idea correct?

Best Regards,
Hirokazu Takahashi

over 4 years ago

0 Michael.Walker over 4 years ago

TI__Mastermind 19720 points

Hi Hirokazu,

The input jitter is measured using a PLL on the scope to track the Channel Link III signal and this is used to sample and overlay the signal to generate an eye diagram. you cannot use a rising edge as the sample point to generate an eye diagram. the jitter is not measured over just 28 bits, it is usually done over 1000's of transitions using persistence on the scope. the 0.53 UI jitter is a typical spec not a max spec.

Regards,

Michael W.

0 HIDEHARU KONDO over 4 years ago

Prodigy 150 points

I'd like to know jitter measurring method using a PLL on the scope.
Does it need analysis software on the scope? For example, "DPOJET" for tektronix's scope.

0 Michael.Walker over 4 years ago in reply to HIDEHARU KONDO

TI__Mastermind 19720 points

Hi,

We use DPOJET on our scopes for the jitter measurement.

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DS92LX1621: Jitter measurement