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Hi,
We are using the TMDS in Sink mode.
We have a certain HDMI2.0 video player that is set to output 4K UHD p 60.
When it is in that mode, and we unplug and replug the HDMI cable, we have no image anymore after replugging.
When checking the TMDS_CLOCK_RATIO_STATUS register, it is set to '1' as expected.
When checking the TMDS181 input clock we measure 148 Mhz, as expected (in 4K60 mode the HDMI source is expected to divide the pixelclock by 4, which is the case)
When checking the TMDS181 output clock however, we measure 37 Mhz (which is 148MHz / 4, this is not as expected, I would expect to see 148MHz here)
When writing the APPLY_RXTX_CHANGES register, the TMDS181 output clock seems to be corrected to 148MHz, and then we have video in the sink again.
I identified two timing cases for the TMDS clock to come up and the TMDS_CLOCK_RATIO register to be set for this player:
1) This happens when the player is set up to output 4K60 and the HDMI cable is plugged in:
- First the TMDS clock comes up at 147MHz
- Later the TMDS_CLOCK_RATIO bit is set while the TMDS clock is still running at 147MHz
2) This happens when the player was already connected and running at 1080p, but the output timing is changed in its GUI to 4K60
- TMDS clock is running at 147MHz
- First the TMDS_CLOCK_RATIO bit is set while the TMDS clock is still running at 147MHz
- Then the clock transmission is suspended for some time (this is a variable time)
- The TMDS clock transmission is resumed at 147MHz
In the first case we always see that the TMDS Clock at the output of the TMDS181 is 37MHz, and we have no image in the sink.
In the second case all is working as expected: the TMDS Clock at the output of the TMDS181 is 147MHz, and we have an image in the sink.
2 questions about this:
1) Why is the output clock divided by 4 compared to the input clock in 4K60 mode? Only the HDMI source should send a divided by 4 clock, the TMDS181 is not supposed to divide it again by 4.
2) Is there a certain sequence that the source should be following when changing to 4K60 mode? for example first generate the TMDS clock, and then write the TMDS_BIT_RATIO register, or the other way around, something I can check that could cause the output clock to be devided by 4 when the TMDS181 is used in sink mode?
