TCA6424A: Not able to detect the device while doing I2C Scan. No ACK from the device. All voltages are proper.

Hello Shiva,

1) What voltages do you see on VCCP and VCCI pins during communication? (please check with o-scope) I know you have them tied to 5V but do you see these voltages fall when you try to communicate or is it stable at 5V all the time. Also check to see what the current going into VCCP is.

2) Can you send us o-scope shots of what the SDA and SCL look like?

3) Just to be sure something silly isn't happening with the PCB board. Have you checked to make sure the trace from the master's SDA line to the TCA device are indeed connect and same goes for the SCL. It is very important to verify these weren't accidentally swapped.

4) What is your master device? (mcu, FPGA?)

5) In the case where the device may be latched, please pull the Reset I/O Pin Low and VERIFY with an Oscope it has reached GND. Then try to get an ACK from the device. You may also try to send 9 clock pulses to the SCL line and then try again to communicate with the device and try to get an ACK.
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I've checked the pin mapping of your device on the schematic to the datasheet and it matches up.

By tying ADDR to GND the Slave address should be 0010 0010 or 22hex which matches what you've stated as well.

-Bobby

1. We are seeing 5V on VCCP and VCCI pins during communication. It is stable at 5V all the time. Please find the attached oscilloscope captures for your reference.
2. Please find the attached oscilloscope captures of SDA and SCL when the RESET is pulled high. There is no ACK from the device.
3. We have checked the PCB board file and confirm that both SDA and SCL lines/traces are connected properly and is not swapped.
4. Our master device is Artix 7 FPGA of AC701 evaluation board.
5. We pulled the RESET pin LOW and captured the SDA and SCL lines while scanning for I2C device. We got the same observation as with RESET pulled high. Please find the attached oscilloscope capture for your reference.

Hey Shiva,

1) What side of the FETS (Q7 and Q8) did you probe the o-scopes on? Side '3' connected to the FPGA or side '2' on the SDA/SCL lines? If you probed on side 3, it is better to probe on side 2 because we want to see what the device sees.

2) Why are the FETs there? What are their intended use?

3) Can you try removing the FETs and shorting the pads so the FPGA is connected directly to the SDA/SCL bus? If so, please test this and see if you can get an ACK.

-Bobby

Hi Bobby,

1) We probed the o-scopes on the PIN 2 side of the FETS (Q7 and Q8).
2) FETs are their to act as level translators. FPGA is giving 3V3 level signals and the device needs 5V level signals as per our design. So the FETs perform the job of level translation and as it can be seen from the captures that they are working fine as expected.

--Shiva

Hi Bobby,

Gentle Reminder!!!

-Shiva

Hey Shiva,

1) Is this an issue that you see on multiple boards or just one board? If this is a repeatable issue, it may tell us the set up is incorrect and not an issue like incorrect soldering/one bad PCB from the lot.

2) Can you also probe directly at pin 28 (reset) and ensure that this pin is not holding low? (it should read 5V) If you can't probe directly on the pin, please probe the point on R3 connecting to pin 28 and NOT R3 to the power supply.

3) Is it possible to change the address by placing a pull up resistor on pin26 (ADDR) and try to access address 23h?

4) On the left of the mosfets, do you have them directly connected to the FPGA or is there other circuitry the SDA/SCL lines are connected to?

5) I would still like to test this without the mosfets there if possible, can you change Vcci/Vccp to 3.3V and remove the mosfets and short the pads of the fets 2 and 3 together?

6) Please get an ammeter and check the current into VCCP.

Thanks,

-Bobby

Hey Bobby,

1) Yes, this is an issue that we are observing on multiple boards.  

2) We probed directly at pin 28 (reset) and ensured that this pin is not holding low. It reads 5V/3.3V depending on the corresponding VCC we are supplying.

3) It is not possible to change the address by placing a pull up resistor on pin26 (ADDR) in our case as for doing that we would need to cut a pcb trace.

4) On the left of the mosfets, we have another translator before the FPGA which translates from 2.5V to 3.3V. We have checked its working, and it is working properly. 

5) We also tested the chip without the mosfets. We changed Vcci/Vccp to 3.3V and removed the mosfets and shorted the pads of the fets 2 and 3 together. The same observation was recorded. 

6) We could not check the current into VCCP as there is no other component between this pin and the voltage rail. Its connected through a PCB trace through which we cannot measure the current.

Thanks,

-Shiva

Hey Shiva,

I don't see any issues with the schematic design, the address you are sending is correct, and the master transmitted waveforms look good. This should be working.

1) You said there are multiple boards experiencing this issue, are all of them having the issue or are some of them working?

2) This may seem a bit of a stretch but is it possible the part is not oriented correctly on the board (pin1 is not mapped to pin1 perhaps soldered on 180 degrees)?

3) When you removed the mosfet and set the Vcc to 3.3V did you pull reset low and release it before trying to send the address? If not please try that.

4) This device also works at 2.5V, can we try to put 2.5V on VCCI/VCCP and bypass the 2.5V to 3.3V translator? I want a direct connection to the FPGA and our device and pull up resistors and nothing else. (Also remember to pull reset low for a second or 2 then try sending the address [please verify using oscope that it has reached GND])

5) Do you have other devices on your board that you can communicate with using I2C?

6) Also, just to rule out anything funny. Can you use a DMM to check continuity on PIN25 and PIN21-24 and PIN26. Then check continuity between PIN25 and GND pin of FPGA.

Hi Bobby,

1) We have 2 boards and both of them are having this issue.

2) The part is correctly placed and soldered properly. We had a soldering touch up work to reconfirm that.

3) Pulling Reset low is also tried. Same observation.

4) There is a direct connection of the device to the FPGA as we are now checking with an Evaluation board and not the actual board of our project. Same observation.

5) We have only one device on this particular I2C Bus. Other devices on other I2C buses have no problems.

6) Continuity checked and found to be OK.

Hi Shiva,

1) I was looking at your oscope pictures again and noticed the SDA lines are falling a little bit then rising back to Vcc during 8th falling edge of SCL. This is likely the SCL line coupling onto the SDA line which is okay in this situation as we sample data during the middle of SCL not the rising or falling edge. (signal integrity is okay).

I am worried that the reset pin may also be pulled low during this (SCL coupling onto reset pin) and causing the device to reset during the data transaction. Could you re-perform trying to get the ACK but place a scope probe on the reset pin. (please also put one on VCCI as it is also sitting next to SDA).

2) Section 10 of the datasheet mentions a power supply requirement. I don't think this is the issue but it would be good to check and rule out. The concern is Vcci/Vccp is being ramped up too slow. Can you probe the power supply pins on the TCA6424A and check to see what the ramp up time (from GND to VCC) is?

3) Can you take a clear high resolution picture of the device on the board for us (or provide the lot number)? I need to be able to read the letters on top of the IC. Also may I ask which vendor you got this part from? From the information you've given me so far, it seems everything should be working. I would like to make sure the device is genuine and not a counterfeit as this could be an issue.

Thanks,
-Bobby

Hi Bobby,

1) We probed the RESET pin during the data transaction and observed that RESET is stable at a logic high level during the whole data transaction time. We also checked VCCI pin during the transaction time and observed that it was stable at 3V3 during the whole transaction time.

2) We probed the VCCI and VCCP pins to see the ramp up times. Following are the captures:

VCCI:

VCCP:

3) We have purchased it online from Mouser Electronics. Kindly find the high resolution picture of the device for your reference:

--Thanks,

Shiva

Hello Shiva,
It looks like you are using Altium. If so, can you send us the project packaged (schematic, pcb, project files, etc) up so we can review it and verify it. You can "+ Connect" to us and we will send you our email link. I would like to review it to make sure it is connected correctly. Also, which pins of the connector are SCL and SDA assume that is in the schematic. If we don't see any problems with the design from the schematic/pcb we may have you send the PCB to us for us to debug. We can exchange shipping information after we "+ Connect"
-Francis Houde

Hello Shiva,

What I am hoping to check is if your layout is correct by checking the layout, for example look at the image below where I show the top layer of the TCA6t424A.  I want to make sure the SCL and SDA lines aren't swapped or if they are connected to an IO or something.