Linux/OMAP5432-EVM: ISS Camera Driver issue: L3 Standard Error: MASTER MPU TARGET ISS (Read): At Address: 0x00000074

/*
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 * Based on "omap4.dtsi"
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/omap.h>

#include "skeleton.dtsi"

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	compatible = "ti,omap5";
	interrupt-parent = <&wakeupgen>;

	aliases {
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		i2c4 = &i2c5;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x0>;

			operating-points = <
				/* kHz    uV */
				1000000 1060000
				1500000 1250000
			>;

			clocks = <&dpll_mpu_ck>;
			clock-names = "cpu";

			clock-latency = <300000>; /* From omap-cpufreq driver */

			/* cooling options */
			cooling-min-level = <0>;
			cooling-max-level = <2>;
			#cooling-cells = <2>; /* min followed by max */
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x1>;
		};
	};

	thermal-zones {
		#include "omap4-cpu-thermal.dtsi"
		#include "omap5-gpu-thermal.dtsi"
		#include "omap5-core-thermal.dtsi"
	};

	timer {
		compatible = "arm,armv7-timer";
		/* PPI secure/nonsecure IRQ */
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
		interrupt-parent = <&gic>;
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
	};

	gic: interrupt-controller@48211000 {
		compatible = "arm,cortex-a15-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48211000 0x1000>,
		      <0x48212000 0x1000>,
		      <0x48214000 0x2000>,
		      <0x48216000 0x2000>;
		interrupt-parent = <&gic>;
	};

	wakeupgen: interrupt-controller@48281000 {
		compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48281000 0x1000>;
		interrupt-parent = <&gic>;
	};

	/*
	 * The soc node represents the soc top level view. It is used for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap4-mpu";
			ti,hwmods = "mpu";
			sram = <&ocmcram>;
		};
	};

	/*
	 * XXX: Use a flat representation of the OMAP3 interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since it will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
		compatible = "ti,omap5-l3-noc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
		reg = <0x44000000 0x2000>,
		      <0x44800000 0x3000>,
		      <0x45000000 0x4000>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

		l4_cfg: l4@4a000000 {
			compatible = "ti,omap5-l4-cfg", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x4a000000 0x22a000>;

			scm_core: scm@2000 {
				compatible = "ti,omap5-scm-core", "simple-bus";
				reg = <0x2000 0x1000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x2000 0x800>;

				scm_conf: scm_conf@0 {
					compatible = "syscon";
					reg = <0x0 0x800>;
					#address-cells = <1>;
					#size-cells = <1>;
				};
			};

			scm_padconf_core: scm@2800 {
				compatible = "ti,omap5-scm-padconf-core",
					     "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x2800 0x800>;

				omap5_pmx_core: pinmux@40 {
					compatible = "ti,omap5-padconf",
						     "pinctrl-single";
					reg = <0x40 0x01b6>;
					#address-cells = <1>;
					#size-cells = <0>;
					#interrupt-cells = <1>;
					interrupt-controller;
					pinctrl-single,register-width = <16>;
					pinctrl-single,function-mask = <0x7fff>;
				};

				omap5_padconf_global: omap5_padconf_global@5a0 {
					compatible = "syscon",
						     "simple-bus";
					reg = <0x5a0 0xec>;
					#address-cells = <1>;
					#size-cells = <1>;

					pbias_regulator: pbias_regulator {
						compatible = "ti,pbias-omap";
						reg = <0x60 0x4>;
						syscon = <&omap5_padconf_global>;
						pbias_mmc_reg: pbias_mmc_omap5 {
							regulator-name = "pbias_mmc_omap5";
							regulator-min-microvolt = <1800000>;
							regulator-max-microvolt = <3000000>;
						};
					};
				};
			};

			cm_core_aon: cm_core_aon@4000 {
				compatible = "ti,omap5-cm-core-aon";
				reg = <0x4000 0x2000>;

				cm_core_aon_clocks: clocks {
					#address-cells = <1>;
					#size-cells = <0>;
				};

				cm_core_aon_clockdomains: clockdomains {
				};
			};

			cm_core: cm_core@8000 {
				compatible = "ti,omap5-cm-core";
				reg = <0x8000 0x3000>;

				cm_core_clocks: clocks {
					#address-cells = <1>;
					#size-cells = <0>;
				};

				cm_core_clockdomains: clockdomains {
				};
			};
		};

		l4_wkup: l4@4ae00000 {
			compatible = "ti,omap5-l4-wkup", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x4ae00000 0x2b000>;

			counter32k: counter@4000 {
				compatible = "ti,omap-counter32k";
				reg = <0x4000 0x40>;
				ti,hwmods = "counter_32k";
			};

			prm: prm@6000 {
				compatible = "ti,omap5-prm";
				reg = <0x6000 0x3000>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

				prm_clocks: clocks {
					#address-cells = <1>;
					#size-cells = <0>;
				};

				prm_clockdomains: clockdomains {
				};
			};

			scrm: scrm@a000 {
				compatible = "ti,omap5-scrm";
				reg = <0xa000 0x2000>;

				scrm_clocks: clocks {
					#address-cells = <1>;
					#size-cells = <0>;
				};

				scrm_clockdomains: clockdomains {
				};
			};

			omap5_pmx_wkup: pinmux@c840 {
				compatible = "ti,omap5-padconf",
					     "pinctrl-single";
				reg = <0xc840 0x0038>;
				#address-cells = <1>;
				#size-cells = <0>;
				#interrupt-cells = <1>;
				interrupt-controller;
				pinctrl-single,register-width = <16>;
				pinctrl-single,function-mask = <0x7fff>;
			};
		};

		ocmcram: ocmcram@40300000 {
			compatible = "mmio-sram";
			reg = <0x40300000 0x20000>; /* 128k */
		};

		sdma: dma-controller@4a056000 {
			compatible = "ti,omap4430-sdma";
			reg = <0x4a056000 0x1000>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			dma-channels = <32>;
			dma-requests = <127>;
		};

		iss: iss@52000000 {
            compatible = "ti,omap4-iss";
            reg = <0x52000000 0x100>, /* top */
                  <0x52001000 0x170>, /* csi2_a_regs1 */
                  <0x52001170 0x020>, /* camerarx_core1 */
                  <0x52001400 0x170>, /* csi2_b_regs1 */
                  <0x52001570 0x020>, /* camerarx_core2 */
                  <0x52002000 0x200>, /* bte */
                  <0x52010000 0x0a0>, /* isp_sys1 */
                  <0x52010400 0x400>, /* isp_resizer */
                  <0x52010800 0x800>, /* isp_ipipe */
                  <0x52011000 0x200>, /* isp_isif */
                  <0x52011200 0x080>; /* isp_ipipeif */
            reg-names = "top",
                        "csi2_a_regs1",
                        "camerarx_core1",
                        "csi2_b_regs1",
                        "camerarx_core2",
                        "bte",
                        "isp_sys1",
                        "isp_resizer",
                        "isp_ipipe",
                        "isp_isif",
                        "isp_ipipeif";
            status = "ok";
            ti,hwmods = "iss";
            interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&ducati_clk_mux_ck>, <&iss_ctrlclk>;
            clock-names = "iss_fck", "iss_ctrlclk";
            dmas = <&sdma 9>, <&sdma 10>, <&sdma 12>, <&sdma 13>;
            dma-names = "1", "2", "3", "4";
        };
        
		gpio1: gpio@4ae10000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4ae10000 0x200>;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio1";
			ti,gpio-always-on;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@48055000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48055000 0x200>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@48057000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48057000 0x200>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio@48059000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48059000 0x200>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio5: gpio@4805b000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805b000 0x200>;
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio5";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio6: gpio@4805d000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805d000 0x200>;
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio6";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio7: gpio@48051000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48051000 0x200>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio7";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio8: gpio@48053000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48053000 0x200>;
			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio8";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpmc: gpmc@50000000 {
			compatible = "ti,omap4430-gpmc";
			reg = <0x50000000 0x1000>;
			#address-cells = <2>;
			#size-cells = <1>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			gpmc,num-cs = <8>;
			gpmc,num-waitpins = <4>;
			ti,hwmods = "gpmc";
			clocks = <&l3_iclk_div>;
			clock-names = "fck";
		};

		i2c1: i2c@48070000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48070000 0x100>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c1";
		};

		i2c2: i2c@48072000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48072000 0x100>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c2";
		};

		i2c3: i2c@48060000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48060000 0x100>;
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c3";
		};

		i2c4: i2c@4807a000 {
			compatible = "ti,omap4-i2c";
			reg = <0x4807a000 0x100>;
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c4";
		};

		i2c5: i2c@4807c000 {
			compatible = "ti,omap4-i2c";
			reg = <0x4807c000 0x100>;
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c5";
		};

		hwspinlock: spinlock@4a0f6000 {
			compatible = "ti,omap4-hwspinlock";
			reg = <0x4a0f6000 0x1000>;
			ti,hwmods = "spinlock";
			#hwlock-cells = <1>;
		};

		mcspi1: spi@48098000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x48098000 0x200>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi1";
			ti,spi-num-cs = <4>;
			dmas = <&sdma 35>,
			       <&sdma 36>,
			       <&sdma 37>,
			       <&sdma 38>,
			       <&sdma 39>,
			       <&sdma 40>,
			       <&sdma 41>,
			       <&sdma 42>;
			dma-names = "tx0", "rx0", "tx1", "rx1",
				    "tx2", "rx2", "tx3", "rx3";
		};

		mcspi2: spi@4809a000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x4809a000 0x200>;
			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi2";
			ti,spi-num-cs = <2>;
			dmas = <&sdma 43>,
			       <&sdma 44>,
			       <&sdma 45>,
			       <&sdma 46>;
			dma-names = "tx0", "rx0", "tx1", "rx1";
		};

		mcspi3: spi@480b8000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480b8000 0x200>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi3";
			ti,spi-num-cs = <2>;
			dmas = <&sdma 15>, <&sdma 16>;
			dma-names = "tx0", "rx0";
		};

		mcspi4: spi@480ba000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480ba000 0x200>;
			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi4";
			ti,spi-num-cs = <1>;
			dmas = <&sdma 70>, <&sdma 71>;
			dma-names = "tx0", "rx0";
		};

		uart1: serial@4806a000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806a000 0x100>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart1";
			clock-frequency = <48000000>;
		};

		uart2: serial@4806c000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806c000 0x100>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart2";
			clock-frequency = <48000000>;
		};

		uart3: serial@48020000 {
			compatible = "ti,omap4-uart";
			reg = <0x48020000 0x100>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart3";
			clock-frequency = <48000000>;
		};

		uart4: serial@4806e000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806e000 0x100>;
			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart4";
			clock-frequency = <48000000>;
		};

		uart5: serial@48066000 {
			compatible = "ti,omap4-uart";
			reg = <0x48066000 0x100>;
			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart5";
			clock-frequency = <48000000>;
		};

		uart6: serial@48068000 {
			compatible = "ti,omap4-uart";
			reg = <0x48068000 0x100>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart6";
			clock-frequency = <48000000>;
		};

		mmc1: mmc@4809c000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x4809c000 0x400>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmc1";
			ti,dual-volt;
			ti,needs-special-reset;
			dmas = <&sdma 61>, <&sdma 62>;
			dma-names = "tx", "rx";
			pbias-supply = <&pbias_mmc_reg>;
		};

		mmc2: mmc@480b4000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480b4000 0x400>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmc2";
			ti,needs-special-reset;
			dmas = <&sdma 47>, <&sdma 48>;
			dma-names = "tx", "rx";
		};

		mmc3: mmc@480ad000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480ad000 0x400>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmc3";
			ti,needs-special-reset;
			dmas = <&sdma 77>, <&sdma 78>;
			dma-names = "tx", "rx";
		};

		mmc4: mmc@480d1000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480d1000 0x400>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmc4";
			ti,needs-special-reset;
			dmas = <&sdma 57>, <&sdma 58>;
			dma-names = "tx", "rx";
		};

		mmc5: mmc@480d5000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480d5000 0x400>;
			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmc5";
			ti,needs-special-reset;
			dmas = <&sdma 59>, <&sdma 60>;
			dma-names = "tx", "rx";
		};

		mmu_dsp: mmu@4a066000 {
			compatible = "ti,omap4-iommu";
			reg = <0x4a066000 0x100>;
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmu_dsp";
		};

		mmu_ipu: mmu@55082000 {
			compatible = "ti,omap4-iommu";
			reg = <0x55082000 0x100>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmu_ipu";
			ti,iommu-bus-err-back;
		};

		keypad: keypad@4ae1c000 {
			compatible = "ti,omap4-keypad";
			reg = <0x4ae1c000 0x400>;
			ti,hwmods = "kbd";
		};

		mcpdm: mcpdm@40132000 {
			compatible = "ti,omap4-mcpdm";
			reg = <0x40132000 0x7f>, /* MPU private access */
			      <0x49032000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mcpdm";
			dmas = <&sdma 65>,
			       <&sdma 66>;
			dma-names = "up_link", "dn_link";
			status = "disabled";
		};

		dmic: dmic@4012e000 {
			compatible = "ti,omap4-dmic";
			reg = <0x4012e000 0x7f>, /* MPU private access */
			      <0x4902e000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "dmic";
			dmas = <&sdma 67>;
			dma-names = "up_link";
			status = "disabled";
		};

		mcbsp1: mcbsp@40122000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40122000 0xff>, /* MPU private access */
			      <0x49022000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp1";
			dmas = <&sdma 33>,
			       <&sdma 34>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		mcbsp2: mcbsp@40124000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40124000 0xff>, /* MPU private access */
			      <0x49024000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp2";
			dmas = <&sdma 17>,
			       <&sdma 18>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		mcbsp3: mcbsp@40126000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40126000 0xff>, /* MPU private access */
			      <0x49026000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp3";
			dmas = <&sdma 19>,
			       <&sdma 20>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		mailbox: mailbox@4a0f4000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x4a0f4000 0x200>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mailbox";
			#mbox-cells = <1>;
			ti,mbox-num-users = <3>;
			ti,mbox-num-fifos = <8>;
			mbox_ipu: mbox_ipu {
				ti,mbox-tx = <0 0 0>;
				ti,mbox-rx = <1 0 0>;
			};
			mbox_dsp: mbox_dsp {
				ti,mbox-tx = <3 0 0>;
				ti,mbox-rx = <2 0 0>;
			};
		};

		timer1: timer@4ae18000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4ae18000 0x80>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer1";
			ti,timer-alwon;
		};

		timer2: timer@48032000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48032000 0x80>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer2";
		};

		timer3: timer@48034000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48034000 0x80>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer3";
		};

		timer4: timer@48036000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48036000 0x80>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer4";
		};

		timer5: timer@40138000 {
			compatible = "ti,omap5430-timer";
			reg = <0x40138000 0x80>,
			      <0x49038000 0x80>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer5";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer6: timer@4013a000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4013a000 0x80>,
			      <0x4903a000 0x80>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer6";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer7: timer@4013c000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4013c000 0x80>,
			      <0x4903c000 0x80>;
			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer7";
			ti,timer-dsp;
		};

		timer8: timer@4013e000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4013e000 0x80>,
			      <0x4903e000 0x80>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer8";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer9: timer@4803e000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4803e000 0x80>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer9";
			ti,timer-pwm;
		};

		timer10: timer@48086000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48086000 0x80>;
			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer10";
			ti,timer-pwm;
		};

		timer11: timer@48088000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48088000 0x80>;
			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer11";
			ti,timer-pwm;
		};

		wdt2: wdt@4ae14000 {
			compatible = "ti,omap5-wdt", "ti,omap3-wdt";
			reg = <0x4ae14000 0x80>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "wd_timer2";
		};

		dmm@4e000000 {
			compatible = "ti,omap5-dmm";
			reg = <0x4e000000 0x800>;
			interrupts = <0 113 0x4>;
			ti,hwmods = "dmm";
		};

		emif1: emif@4c000000 {
			compatible	= "ti,emif-4d5";
			ti,hwmods	= "emif1";
			ti,no-idle-on-init;
			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
			reg = <0x4c000000 0x400>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};

		emif2: emif@4d000000 {
			compatible	= "ti,emif-4d5";
			ti,hwmods	= "emif2";
			ti,no-idle-on-init;
			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
			reg = <0x4d000000 0x400>;
			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};

		omap_control_usb2phy: control-phy@4a002300 {
			compatible = "ti,control-phy-usb2";
			reg = <0x4a002300 0x4>;
			reg-names = "power";
		};

		omap_control_usb3phy: control-phy@4a002370 {
			compatible = "ti,control-phy-pipe3";
			reg = <0x4a002370 0x4>;
			reg-names = "power";
		};

		usb3: omap_dwc3@4a020000 {
			compatible = "ti,dwc3";
			ti,hwmods = "usb_otg_ss";
			reg = <0x4a020000 0x10000>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <1>;
			utmi-mode = <2>;
			ranges;
			dwc3@4a030000 {
				compatible = "snps,dwc3";
				reg = <0x4a030000 0x10000>;
				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&usb2_phy>, <&usb3_phy>;
				phy-names = "usb2-phy", "usb3-phy";
				dr_mode = "peripheral";
				tx-fifo-resize;
			};
		};

		ocp2scp@4a080000 {
			compatible = "ti,omap-ocp2scp";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x4a080000 0x20>;
			ranges;
			ti,hwmods = "ocp2scp1";
			usb2_phy: usb2phy@4a084000 {
				compatible = "ti,omap-usb2";
				reg = <0x4a084000 0x7c>;
				ctrl-module = <&omap_control_usb2phy>;
				clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
				clock-names = "wkupclk", "refclk";
				#phy-cells = <0>;
			};

			usb3_phy: usb3phy@4a084400 {
				compatible = "ti,omap-usb3";
				reg = <0x4a084400 0x80>,
				      <0x4a084800 0x64>,
				      <0x4a084c00 0x40>;
				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
				ctrl-module = <&omap_control_usb3phy>;
				clocks = <&usb_phy_cm_clk32k>,
					 <&sys_clkin>,
					 <&usb_otg_ss_refclk960m>;
				clock-names =	"wkupclk",
						"sysclk",
						"refclk";
				#phy-cells = <0>;
			};
		};

		usbhstll: usbhstll@4a062000 {
			compatible = "ti,usbhs-tll";
			reg = <0x4a062000 0x1000>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "usb_tll_hs";
		};

		usbhshost: usbhshost@4a064000 {
			compatible = "ti,usbhs-host";
			reg = <0x4a064000 0x800>;
			ti,hwmods = "usb_host_hs";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			clocks = <&l3init_60m_fclk>,
				 <&xclk60mhsp1_ck>,
				 <&xclk60mhsp2_ck>;
			clock-names = "refclk_60m_int",
				      "refclk_60m_ext_p1",
				      "refclk_60m_ext_p2";

			usbhsohci: ohci@4a064800 {
				compatible = "ti,ohci-omap3";
				reg = <0x4a064800 0x400>;
				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			};

			usbhsehci: ehci@4a064c00 {
				compatible = "ti,ehci-omap";
				reg = <0x4a064c00 0x400>;
				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		bandgap: bandgap@4a0021e0 {
			reg = <0x4a0021e0 0xc
			       0x4a00232c 0xc
			       0x4a002380 0x2c
			       0x4a0023C0 0x3c>;
			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
			compatible = "ti,omap5430-bandgap";

			#thermal-sensor-cells = <1>;
		};

		omap_control_sata: control-phy@4a002374 {
			compatible = "ti,control-phy-pipe3";
			reg = <0x4a002374 0x4>;
			reg-names = "power";
			clocks = <&sys_clkin>;
			clock-names = "sysclk";
		};

		/* OCP2SCP3 */
		ocp2scp@4a090000 {
			compatible = "ti,omap-ocp2scp";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x4a090000 0x20>;
			ranges;
			ti,hwmods = "ocp2scp3";
			sata_phy: phy@4a096000 {
				compatible = "ti,phy-pipe3-sata";
				reg = <0x4A096000 0x80>, /* phy_rx */
				      <0x4A096400 0x64>, /* phy_tx */
				      <0x4A096800 0x40>; /* pll_ctrl */
				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
				ctrl-module = <&omap_control_sata>;
				clocks = <&sys_clkin>, <&sata_ref_clk>;
				clock-names = "sysclk", "refclk";
				#phy-cells = <0>;
			};
		};

		sata: sata@4a141100 {
			compatible = "snps,dwc-ahci";
			reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&sata_phy>;
			phy-names = "sata-phy";
			clocks = <&sata_ref_clk>;
			ti,hwmods = "sata";
		};

		dss: dss@58000000 {
			compatible = "ti,omap5-dss";
			reg = <0x58000000 0x80>;
			status = "disabled";
			ti,hwmods = "dss_core";
			clocks = <&dss_dss_clk>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			dispc@58001000 {
				compatible = "ti,omap5-dispc";
				reg = <0x58001000 0x1000>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
				ti,hwmods = "dss_dispc";
				clocks = <&dss_dss_clk>;
				clock-names = "fck";
			};

			rfbi: encoder@58002000  {
				compatible = "ti,omap5-rfbi";
				reg = <0x58002000 0x100>;
				status = "disabled";
				ti,hwmods = "dss_rfbi";
				clocks = <&dss_dss_clk>, <&l3_iclk_div>;
				clock-names = "fck", "ick";
			};

			dsi1: encoder@58004000 {
				compatible = "ti,omap5-dsi";
				reg = <0x58004000 0x200>,
				      <0x58004200 0x40>,
				      <0x58004300 0x40>;
				reg-names = "proto", "phy", "pll";
				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
				ti,hwmods = "dss_dsi1";
				clocks = <&dss_dss_clk>, <&dss_sys_clk>;
				clock-names = "fck", "sys_clk";
			};

			dsi2: encoder@58005000 {
				compatible = "ti,omap5-dsi";
				reg = <0x58009000 0x200>,
				      <0x58009200 0x40>,
				      <0x58009300 0x40>;
				reg-names = "proto", "phy", "pll";
				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
				ti,hwmods = "dss_dsi2";
				clocks = <&dss_dss_clk>, <&dss_sys_clk>;
				clock-names = "fck", "sys_clk";
			};

			hdmi: encoder@58060000 {
				compatible = "ti,omap5-hdmi";
				reg = <0x58040000 0x200>,
				      <0x58040200 0x80>,
				      <0x58040300 0x80>,
				      <0x58060000 0x19000>;
				reg-names = "wp", "pll", "phy", "core";
				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
				ti,hwmods = "dss_hdmi";
				clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
				clock-names = "fck", "sys_clk";
				dmas = <&sdma 76>;
				dma-names = "audio_tx";
			};
		};

		abb_mpu: regulator-abb-mpu {
			compatible = "ti,abb-v2";
			regulator-name = "abb_mpu";
			#address-cells = <0>;
			#size-cells = <0>;
			clocks = <&sys_clkin>;
			ti,settling-time = <50>;
			ti,clock-cycles = <16>;

			reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
			      <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
			reg-names = "base-address", "int-address",
				    "efuse-address", "ldo-address";
			ti,tranxdone-status-mask = <0x80>;
			/* LDOVBBMPU_MUX_CTRL */
			ti,ldovbb-override-mask = <0x400>;
			/* LDOVBBMPU_VSET_OUT */
			ti,ldovbb-vset-mask = <0x1F>;

			/*
			 * NOTE: only FBB mode used but actual vset will
			 * determine final biasing
			 */
			ti,abb_info = <
			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
			1060000		0	0x0	0 0x02000000 0x01F00000
			1250000		0	0x4	0 0x02000000 0x01F00000
			>;
		};

		abb_mm: regulator-abb-mm {
			compatible = "ti,abb-v2";
			regulator-name = "abb_mm";
			#address-cells = <0>;
			#size-cells = <0>;
			clocks = <&sys_clkin>;
			ti,settling-time = <50>;
			ti,clock-cycles = <16>;

			reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
			      <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
			reg-names = "base-address", "int-address",
				    "efuse-address", "ldo-address";
			ti,tranxdone-status-mask = <0x80000000>;
			/* LDOVBBMM_MUX_CTRL */
			ti,ldovbb-override-mask = <0x400>;
			/* LDOVBBMM_VSET_OUT */
			ti,ldovbb-vset-mask = <0x1F>;

			/*
			 * NOTE: only FBB mode used but actual vset will
			 * determine final biasing
			 */
			ti,abb_info = <
			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
			1025000		0	0x0	0 0x02000000 0x01F00000
			1120000		0	0x4	0 0x02000000 0x01F00000
			>;
		};
	};
};

&cpu_thermal {
	polling-delay = <500>; /* milliseconds */
};

/include/ "omap54xx-clocks.dtsi"

/*
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "omap5.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "TI OMAP5 uEVM board";
	compatible = "ti,omap5-uevm", "ti,omap5";

	memory {
		device_type = "memory";
		reg = <0x80000000 0x7F000000>; /* 2032 MB */
	};

	aliases {
		display0 = &hdmi0;
	};

	vmmcsd_fixed: fixedregulator-mmcsd {
		compatible = "regulator-fixed";
		regulator-name = "vmmcsd_fixed";
		regulator-min-microvolt = <3000000>;
		regulator-max-microvolt = <3000000>;
	};

	mmc3_pwrseq: sdhci0_pwrseq {
		compatible = "mmc-pwrseq-simple";
		clocks = <&clk32kgaudio>;
		clock-names = "ext_clock";
	};

	vmmcsdio_fixed: fixedregulator-mmcsdio {
		compatible = "regulator-fixed";
		regulator-name = "vmmcsdio_fixed";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		gpio = <&gpio5 12 GPIO_ACTIVE_HIGH>;	/* gpio140 WLAN_EN */
		enable-active-high;
		startup-delay-us = <70000>;
		pinctrl-names = "default";
		pinctrl-0 = <&wlan_pins>;
	};

	/* HS USB Host PHY on PORT 2 */
	hsusb2_phy: hsusb2_phy {
		compatible = "usb-nop-xceiv";
		reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */
		clocks = <&auxclk1_ck>;
		clock-names = "main_clk";
		clock-frequency = <19200000>;
	};

	/* HS USB Host PHY on PORT 3 */
	hsusb3_phy: hsusb3_phy {
		compatible = "usb-nop-xceiv";
		reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */
	};

	leds {
		compatible = "gpio-leds";
		led@1 {
			label = "omap5:blue:usr1";
			gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */
			linux,default-trigger = "heartbeat";
			default-state = "off";
		};
	};

	tpd12s015: encoder@0 {
		compatible = "ti,tpd12s015";

		pinctrl-names = "default";
		pinctrl-0 = <&tpd12s015_pins>;

		gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>,	/* TCA6424A P01, CT CP HPD */
			<&gpio9 1 GPIO_ACTIVE_HIGH>,	/* TCA6424A P00, LS OE */
			<&gpio7 1 GPIO_ACTIVE_HIGH>;	/* GPIO 193, HPD */

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				tpd12s015_in: endpoint@0 {
					remote-endpoint = <&hdmi_out>;
				};
			};

			port@1 {
				reg = <1>;

				tpd12s015_out: endpoint@0 {
					remote-endpoint = <&hdmi_connector_in>;
				};
			};
		};
	};

	hdmi0: connector@0 {
		compatible = "hdmi-connector";
		label = "hdmi";

		type = "b";

		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&tpd12s015_out>;
			};
		};
	};

	sound: sound {
		compatible = "ti,abe-twl6040";
		ti,model = "omap5-uevm";

		ti,mclk-freq = <19200000>;

		ti,mcpdm = <&mcpdm>;

		ti,twl6040 = <&twl6040>;

		/* Audio routing */
		ti,audio-routing =
			"Headset Stereophone", "HSOL",
			"Headset Stereophone", "HSOR",
			"Line Out", "AUXL",
			"Line Out", "AUXR",
			"HSMIC", "Headset Mic",
			"Headset Mic", "Headset Mic Bias",
			"AFML", "Line In",
			"AFMR", "Line In";
	};
};

&omap5_pmx_core {
	pinctrl-names = "default";
	pinctrl-0 = <
			&usbhost_pins
			&led_gpio_pins
	>;

	twl6040_pins: pinmux_twl6040_pins {
		pinctrl-single,pins = <
			0x17e (PIN_OUTPUT | MUX_MODE6)	/* mcspi1_somi.gpio5_141 */
		>;
	};

	mcpdm_pins: pinmux_mcpdm_pins {
		pinctrl-single,pins = <
			0x142 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_clks.abe_clks */
			0x15c (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abemcpdm_ul_data.abemcpdm_ul_data */
			0x15e (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abemcpdm_dl_data.abemcpdm_dl_data */
			0x160 (PIN_INPUT_PULLUP | MUX_MODE0)	/* abemcpdm_frame.abemcpdm_frame */
			0x162 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abemcpdm_lb_clk.abemcpdm_lb_clk */
		>;
	};

	mcbsp1_pins: pinmux_mcbsp1_pins {
		pinctrl-single,pins = <
			0x14c (PIN_INPUT | MUX_MODE1)		/* abedmic_clk2.abemcbsp1_fsx */
			0x14e (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* abedmic_clk3.abemcbsp1_dx */
			0x150 (PIN_INPUT | MUX_MODE1)		/* abeslimbus1_clock.abemcbsp1_clkx */
			0x152 (PIN_INPUT_PULLDOWN | MUX_MODE1)	/* abeslimbus1_data.abemcbsp1_dr */
		>;
	};

	mcbsp2_pins: pinmux_mcbsp2_pins {
		pinctrl-single,pins = <
			0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abemcbsp2_dr.abemcbsp2_dr */
			0x156 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* abemcbsp2_dx.abemcbsp2_dx */
			0x158 (PIN_INPUT | MUX_MODE0)		/* abemcbsp2_fsx.abemcbsp2_fsx */
			0x15a (PIN_INPUT | MUX_MODE0)		/* abemcbsp2_clkx.abemcbsp2_clkx */
		>;
	};

	i2c1_pins: pinmux_i2c1_pins {
		pinctrl-single,pins = <
			0x1b2 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_scl */
			0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_sda */
		>;
	};
	
	i2c3_pins: pinmux_i2c3_pins {
		pinctrl-single,pins = <
			OMAP5_IOPAD(0x17A, PIN_INPUT | MUX_MODE0)		/* i2c3_scl */
			OMAP5_IOPAD(0x17C, PIN_INPUT | MUX_MODE0)		/* i2c3_sda */
			
			OMAP5_IOPAD(0x170, PIN_OUTPUT | MUX_MODE6)		/* gpio8_226.reset */
			OMAP5_IOPAD(0x16C, PIN_OUTPUT | MUX_MODE6)		/* gpio8_224.shutter */
			OMAP5_IOPAD(0x16E, PIN_OUTPUT | MUX_MODE6)		/* gpio8_225.strobe */
			OMAP5_IOPAD(0x056, PIN_OUTPUT | MUX_MODE6)		/* gpio1_wk13.shutdowm */
			
		>;
	};
	
	
	
	iss_csi21_pins: pinmux_iss_csi21_pins {
		pinctrl-single,pins = <
			OMAP5_IOPAD(0x158, PIN_INPUT | MUX_MODE0)		/* csiporta_lane0x */
			OMAP5_IOPAD(0x15A, PIN_INPUT | MUX_MODE0)		/* csiporta_lane0y */
			OMAP5_IOPAD(0x15E, PIN_INPUT | MUX_MODE0)		/* csiporta_lane1x */
			OMAP5_IOPAD(0x15C, PIN_INPUT | MUX_MODE0)		/* csiporta_lane1y */
			OMAP5_IOPAD(0x168, PIN_INPUT | MUX_MODE0)		/* csiporta_lane4x */
			OMAP5_IOPAD(0x16A, PIN_INPUT | MUX_MODE0)		/* csiporta_lane4y */
		>;
	};

	i2c5_pins: pinmux_i2c5_pins {
		pinctrl-single,pins = <
			0x186 (PIN_INPUT | MUX_MODE0)		/* i2c5_scl */
			0x188 (PIN_INPUT | MUX_MODE0)		/* i2c5_sda */
		>;
	};

	mcspi2_pins: pinmux_mcspi2_pins {
		pinctrl-single,pins = <
			0xbc (PIN_INPUT | MUX_MODE0)		/*  mcspi2_clk */
			0xbe (PIN_INPUT | MUX_MODE0)		/*  mcspi2_simo */
			0xc0 (PIN_INPUT_PULLUP | MUX_MODE0)	/*  mcspi2_somi */
			0xc2 (PIN_OUTPUT | MUX_MODE0)		/*  mcspi2_cs0 */
		>;
	};

	mcspi3_pins: pinmux_mcspi3_pins {
		pinctrl-single,pins = <
			0x78 (PIN_INPUT | MUX_MODE1)		/*  mcspi3_somi */
			0x7a (PIN_INPUT | MUX_MODE1)		/*  mcspi3_cs0 */
			0x7c (PIN_INPUT | MUX_MODE1)		/*  mcspi3_simo */
			0x7e (PIN_INPUT | MUX_MODE1)		/*  mcspi3_clk */
		>;
	};

	mmc3_pins: pinmux_mmc3_pins {
		pinctrl-single,pins = <
			OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */
			OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */
			OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */
			OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */
			OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */
			OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */
		>;
	};

	wlan_pins: pinmux_wlan_pins {
		pinctrl-single,pins = <
			OMAP5_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE6) /* mcspi1_clk.gpio5_140 */
		>;
	};

	usbhost_pins: pinmux_usbhost_pins {
		pinctrl-single,pins = <
			0x84 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */
			0x86 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */

			0x19e (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */
			0x1a0 (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */

			0x70 (PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */
			0x6e (PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */
		>;
	};

	led_gpio_pins: pinmux_led_gpio_pins {
		pinctrl-single,pins = <
			0x196 (PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */
		>;
	};

	uart1_pins: pinmux_uart1_pins {
		pinctrl-single,pins = <
			0x60 (PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */
			0x62 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */
			0x64 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */
			0x66 (PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */
		>;
	};

	uart3_pins: pinmux_uart3_pins {
		pinctrl-single,pins = <
			0x19a (PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */
			0x19c (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */
		>;
	};

	uart5_pins: pinmux_uart5_pins {
		pinctrl-single,pins = <
			0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */
			0x172 (PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */
			0x174 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */
			0x176 (PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */
		>;
	};

	dss_hdmi_pins: pinmux_dss_hdmi_pins {
		pinctrl-single,pins = <
			0x0fc (PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_cec.hdmi_cec */
			0x100 (PIN_INPUT | MUX_MODE0)	/* hdmi_ddc_scl.hdmi_ddc_scl */
			0x102 (PIN_INPUT | MUX_MODE0)	/* hdmi_ddc_sda.hdmi_ddc_sda */
		>;
	};

	tpd12s015_pins: pinmux_tpd12s015_pins {
		pinctrl-single,pins = <
			0x0fe (PIN_INPUT_PULLDOWN | MUX_MODE6)	/* hdmi_hpd.gpio7_193 */
		>;
	};
};

&omap5_pmx_wkup {
	pinctrl-names = "default";
	pinctrl-0 = <
			&usbhost_wkup_pins
	>;

	usbhost_wkup_pins: pinmux_usbhost_wkup_pins {
		pinctrl-single,pins = <
			0x1A (PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */
		>;
	};

	wlcore_irq_pin: pinmux_wlcore_irq_pin {
		pinctrl-single,pins = <
			OMAP5_IOPAD(0x040, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE6)	/* llia_wakereqin.gpio1_wk14 */
		>;
	};
};

&mmc1 {
	vmmc-supply = <&ldo9_reg>;
	bus-width = <4>;
};

&mmc2 {
	vmmc-supply = <&vmmcsd_fixed>;
	bus-width = <8>;
	ti,non-removable;
};

&mmc3 {
	vmmc-supply = <&vmmcsdio_fixed>;
	mmc-pwrseq = <&mmc3_pwrseq>;
	bus-width = <4>;
	non-removable;
	cap-power-off-card;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc3_pins &wlcore_irq_pin>;
	interrupts-extended = <&gic GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
			       &omap5_pmx_core 0x168>;

	#address-cells = <1>;
	#size-cells = <0>;
	wlcore: wlcore@2 {
		compatible = "ti,wl1271";
		reg = <2>;
		interrupt-parent = <&gpio1>;
		interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;	/* gpio 14 */
		ref-clock-frequency = <26000000>;
	};
};

&mmc4 {
	status = "disabled";
};

&mmc5 {
	status = "disabled";
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;

	clock-frequency = <400000>;

	palmas: palmas@48 {
		compatible = "ti,palmas";
		interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
		reg = <0x48>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,system-power-controller;

		extcon_usb3: palmas_usb {
			compatible = "ti,palmas-usb-vid";
			ti,enable-vbus-detection;
			ti,enable-id-detection;
			ti,wakeup;
		};

		clk32kgaudio: palmas_clk32k@1 {
			compatible = "ti,palmas-clk32kgaudio";
			#clock-cells = <0>;
		};

		palmas_pmic {
			compatible = "ti,palmas-pmic";
			interrupt-parent = <&palmas>;
			interrupts = <14 IRQ_TYPE_NONE>;
			interrupt-name = "short-irq";

			ti,ldo6-vibrator;

			regulators {
				smps123_reg: smps123 {
					/* VDD_OPP_MPU */
					regulator-name = "smps123";
					regulator-min-microvolt = < 600000>;
					regulator-max-microvolt = <1500000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps45_reg: smps45 {
					/* VDD_OPP_MM */
					regulator-name = "smps45";
					regulator-min-microvolt = < 600000>;
					regulator-max-microvolt = <1310000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps6_reg: smps6 {
					/* VDD_DDR3 - over VDD_SMPS6 */
					regulator-name = "smps6";
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps7_reg: smps7 {
					/* VDDS_1v8_OMAP over VDDS_1v8_MAIN */
					regulator-name = "smps7";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps8_reg: smps8 {
					/* VDD_OPP_CORE */
					regulator-name = "smps8";
					regulator-min-microvolt = < 600000>;
					regulator-max-microvolt = <1310000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps9_reg: smps9 {
					/* VDDA_2v1_AUD over VDD_2v1 */
					regulator-name = "smps9";
					regulator-min-microvolt = <2100000>;
					regulator-max-microvolt = <2100000>;
					ti,smps-range = <0x80>;
				};

				smps10_out2_reg: smps10_out2 {
					/* VBUS_5V_OTG */
					regulator-name = "smps10_out2";
					regulator-min-microvolt = <5000000>;
					regulator-max-microvolt = <5000000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps10_out1_reg: smps10_out1 {
					/* VBUS_5V_OTG */
					regulator-name = "smps10_out1";
					regulator-min-microvolt = <5000000>;
					regulator-max-microvolt = <5000000>;
				};

				ldo1_reg: ldo1 {
					/* VDDAPHY_CAM: vdda_csiport */
					regulator-name = "ldo1";
					regulator-min-microvolt = <1500000>;
					regulator-max-microvolt = <1800000>;
				};

				ldo2_reg: ldo2 {
					/* VCC_2V8_DISP: Does not go anywhere */
					regulator-name = "ldo2";
					regulator-min-microvolt = <2800000>;
					regulator-max-microvolt = <2800000>;
					/* Unused */
					status = "disabled";
				};

				ldo3_reg: ldo3 {
					/* VDDAPHY_MDM: vdda_lli */
					regulator-name = "ldo3";
					regulator-min-microvolt = <1500000>;
					regulator-max-microvolt = <1500000>;
					regulator-boot-on;
					/* Only if Modem is used */
					status = "disabled";
				};

				ldo4_reg: ldo4 {
					/* VDDAPHY_DISP: vdda_dsiport/hdmi */
					regulator-name = "ldo4";
					regulator-min-microvolt = <1500000>;
					regulator-max-microvolt = <1800000>;
				};

				ldo5_reg: ldo5 {
					/* VDDA_1V8_PHY: usb/sata/hdmi.. */
					regulator-name = "ldo5";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo6_reg: ldo6 {
					/* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */
					regulator-name = "ldo6";
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo7_reg: ldo7 {
					/* VDD_VPP: vpp1 */
					regulator-name = "ldo7";
					regulator-min-microvolt = <2000000>;
					regulator-max-microvolt = <2000000>;
					/* Only for efuse reprograming! */
					status = "disabled";
				};

				ldo8_reg: ldo8 {
					/* VDD_3v0: Does not go anywhere */
					regulator-name = "ldo8";
					regulator-min-microvolt = <3000000>;
					regulator-max-microvolt = <3000000>;
					regulator-boot-on;
					/* Unused */
					status = "disabled";
				};

				ldo9_reg: ldo9 {
					/* VCC_DV_SDIO: vdds_sdcard */
					regulator-name = "ldo9";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <3000000>;
					regulator-boot-on;
				};

				ldoln_reg: ldoln {
					/* VDDA_1v8_REF: vdds_osc/mm_l4per.. */
					regulator-name = "ldoln";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldousb_reg: ldousb {
					/* VDDA_3V_USB: VDDA_USBHS33 */
					regulator-name = "ldousb";
					regulator-min-microvolt = <3250000>;
					regulator-max-microvolt = <3250000>;
					regulator-always-on;
					regulator-boot-on;
				};

				regen3_reg: regen3 {
					/* REGEN3 controls LDO9 supply to card */
					regulator-name = "regen3";
					regulator-always-on;
					regulator-boot-on;
				};
			};
		};
	};

	twl6040: twl@4b {
		compatible = "ti,twl6040";
		reg = <0x4b>;

		pinctrl-names = "default";
		pinctrl-0 = <&twl6040_pins>;

		interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */
		ti,audpwron-gpio = <&gpio5 13 0>;  /* gpio line 141 */

		vio-supply = <&smps7_reg>;
		v2v1-supply = <&smps9_reg>;
		enable-active-high;

		clocks = <&clk32kgaudio>;
		clock-names = "clk32k";
	};
};

&i2c5 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c5_pins>;

	clock-frequency = <400000>;

	gpio9: gpio@22 {
		compatible = "ti,tca6424";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&mcpdm {
	pinctrl-names = "default";
	pinctrl-0 = <&mcpdm_pins>;
	status = "okay";
};

&mcbsp1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcbsp1_pins>;
	status = "okay";
};

&mcbsp2 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcbsp2_pins>;
	status = "okay";
};

&usbhshost {
	port2-mode = "ehci-hsic";
	port3-mode = "ehci-hsic";
};

&usbhsehci {
	phys = <0 &hsusb2_phy &hsusb3_phy>;
};

&usb3 {
	extcon = <&extcon_usb3>;
	vbus-supply = <&smps10_out1_reg>;
};

&mcspi1 {

};

&mcspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcspi2_pins>;
};

&mcspi3 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcspi3_pins>;
};

&uart1 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart1_pins>;
};

&uart3 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart3_pins>;
};

&uart5 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart5_pins>;
};

&cpu0 {
	cpu0-supply = <&smps123_reg>;
};

&dss {
	status = "ok";
};

&hdmi {
	status = "ok";
	vdda-supply = <&ldo4_reg>;

	pinctrl-names = "default";
	pinctrl-0 = <&dss_hdmi_pins>;

	port {
		hdmi_out: endpoint {
			remote-endpoint = <&tpd12s015_in>;
		};
	};
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_pins>;
	status = "ok";

	clock-frequency = <100000>;

	ov5640_1_camera: camera@3c {
		compatible = "omnivision,ov5640";
		status = "ok";
		reg = <0x3c>;

		pwdn-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;	// gpio1_13 - power down
		reset-gpios = <&gpio8 2 GPIO_ACTIVE_LOW>;	// gpio8_226 - reset

		clocks = <&auxclk1_ck>;
		
		port {
			ov5640_1_cam_ep: endpoint {
				clock-lanes = <4>;
				data-lanes = <0 1>;
				remote-endpoint = <&csi2a_ep>;
			};
		};
	};
};


&iss {
    status = "ok";

    pinctrl-names = "default";
    pinctrl-0 = <&iss_csi21_pins>;

    ports {
        port@0 {
            reg = <0>;
            csi2a_ep: endpoint {
                remote-endpoint = <&ov5640_1_cam_ep>;
                clock-lanes = <4>;
                data-lanes = <0 1>;
                crc = <0>;
                lane-polarities = <0 0 0>;
            };
        };
    };
};

/*
 * Device Tree Source for OMAP5 clock data
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
&cm_core_aon_clocks {
	pad_clks_src_ck: pad_clks_src_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <12000000>;
	};
	
	dpll_core_m5x2_ck: dpll_core_m5x2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <31>;
		ti,autoidle-shift = <8>;
		reg = <0x013c>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	div_core_ck: div_core_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_core_m5x2_ck>;
		reg = <0x0100>;
		ti,max-div = <2>;
	};

	pad_clks_ck: pad_clks_ck {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&pad_clks_src_ck>;
		ti,bit-shift = <8>;
		reg = <0x0108>;
	};

	secure_32k_clk_src_ck: secure_32k_clk_src_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <32768>;
	};

	slimbus_src_clk: slimbus_src_clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <12000000>;
	};

	slimbus_clk: slimbus_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&slimbus_src_clk>;
		ti,bit-shift = <10>;
		reg = <0x0108>;
	};

	sys_32k_ck: sys_32k_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <32768>;
	};

	virt_12000000_ck: virt_12000000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <12000000>;
	};

	virt_13000000_ck: virt_13000000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <13000000>;
	};

	virt_16800000_ck: virt_16800000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <16800000>;
	};

	virt_19200000_ck: virt_19200000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <19200000>;
	};

	virt_26000000_ck: virt_26000000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <26000000>;
	};

	virt_27000000_ck: virt_27000000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <27000000>;
	};

	virt_38400000_ck: virt_38400000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <38400000>;
	};

	xclk60mhsp1_ck: xclk60mhsp1_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <60000000>;
	};

	xclk60mhsp2_ck: xclk60mhsp2_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <60000000>;
	};

	dpll_abe_ck: dpll_abe_ck {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-m4xen-clock";
		clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
		reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
	};

	dpll_abe_x2_ck: dpll_abe_x2_ck {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-x2-clock";
		clocks = <&dpll_abe_ck>;
	};

	dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_abe_x2_ck>;
		ti,max-div = <31>;
		reg = <0x01f0>;
		ti,index-starts-at-one;
	};

	abe_24m_fclk: abe_24m_fclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_abe_m2x2_ck>;
		clock-mult = <1>;
		clock-div = <8>;
	};

	abe_clk: abe_clk {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_abe_m2x2_ck>;
		ti,max-div = <4>;
		reg = <0x0108>;
		ti,index-power-of-two;
	};

	abe_iclk: abe_iclk {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&aess_fclk>;
		ti,bit-shift = <24>;
		reg = <0x0528>;
		ti,dividers = <2>, <1>;
	};

	abe_lp_clk_div: abe_lp_clk_div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_abe_m2x2_ck>;
		clock-mult = <1>;
		clock-div = <16>;
	};

	dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_abe_x2_ck>;
		ti,max-div = <31>;
		reg = <0x01f4>;
		ti,index-starts-at-one;
	};

	dpll_core_byp_mux: dpll_core_byp_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
		ti,bit-shift = <23>;
		reg = <0x012c>;
	};

	dpll_core_ck: dpll_core_ck {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-core-clock";
		clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
		reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
	};

	dpll_core_x2_ck: dpll_core_x2_ck {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-x2-clock";
		clocks = <&dpll_core_ck>;
	};

	dpll_core_h21x2_ck: dpll_core_h21x2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		reg = <0x0150>;
		ti,index-starts-at-one;
	};

	c2c_fclk: c2c_fclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_core_h21x2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	c2c_iclk: c2c_iclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&c2c_fclk>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	dpll_core_h11x2_ck: dpll_core_h11x2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		reg = <0x0138>;
		ti,index-starts-at-one;
	};

	dpll_core_h12x2_ck: dpll_core_h12x2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		reg = <0x013c>;
		ti,index-starts-at-one;
	};

	dpll_core_h13x2_ck: dpll_core_h13x2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		reg = <0x0140>;
		ti,index-starts-at-one;
	};

	dpll_core_h14x2_ck: dpll_core_h14x2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		reg = <0x0144>;
		ti,index-starts-at-one;
	};

	dpll_core_h22x2_ck: dpll_core_h22x2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		reg = <0x0154>;
		ti,index-starts-at-one;
	};

	dpll_core_h23x2_ck: dpll_core_h23x2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		reg = <0x0158>;
		ti,index-starts-at-one;
	};

	dpll_core_h24x2_ck: dpll_core_h24x2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		reg = <0x015c>;
		ti,index-starts-at-one;
	};

	dpll_core_m2_ck: dpll_core_m2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_core_ck>;
		ti,max-div = <31>;
		reg = <0x0130>;
		ti,index-starts-at-one;
	};

	dpll_core_m3x2_ck: dpll_core_m3x2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <31>;
		reg = <0x0134>;
		ti,index-starts-at-one;
	};

	iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_core_h12x2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll_iva_byp_mux: dpll_iva_byp_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
		ti,bit-shift = <23>;
		reg = <0x01ac>;
	};

	dpll_iva_ck: dpll_iva_ck {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-clock";
		clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
		reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
	};

	dpll_iva_x2_ck: dpll_iva_x2_ck {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-x2-clock";
		clocks = <&dpll_iva_ck>;
	};

	dpll_iva_h11x2_ck: dpll_iva_h11x2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_iva_x2_ck>;
		ti,max-div = <63>;
		reg = <0x01b8>;
		ti,index-starts-at-one;
	};

	dpll_iva_h12x2_ck: dpll_iva_h12x2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_iva_x2_ck>;
		ti,max-div = <63>;
		reg = <0x01bc>;
		ti,index-starts-at-one;
	};

	mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_core_h12x2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll_mpu_ck: dpll_mpu_ck {
		#clock-cells = <0>;
		compatible = "ti,omap5-mpu-dpll-clock";
		clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
		reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
	};

	dpll_mpu_m2_ck: dpll_mpu_m2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_mpu_ck>;
		ti,max-div = <31>;
		reg = <0x0170>;
		ti,index-starts-at-one;
	};

	per_dpll_hs_clk_div: per_dpll_hs_clk_div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_abe_m3x2_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_abe_m3x2_ck>;
		clock-mult = <1>;
		clock-div = <3>;
	};

	l3_iclk_div: l3_iclk_div {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		ti,max-div = <2>;
		ti,bit-shift = <4>;
		reg = <0x100>;
		clocks = <&dpll_core_h12x2_ck>;
		ti,index-power-of-two;
	};

	gpu_l3_iclk: gpu_l3_iclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&l3_iclk_div>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	l4_root_clk_div: l4_root_clk_div {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		ti,max-div = <2>;
		ti,bit-shift = <8>;
		reg = <0x100>;
		clocks = <&l3_iclk_div>;
		ti,index-power-of-two;
	};

	slimbus1_slimbus_clk: slimbus1_slimbus_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&slimbus_clk>;
		ti,bit-shift = <11>;
		reg = <0x0560>;
	};

	aess_fclk: aess_fclk {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&abe_clk>;
		ti,bit-shift = <24>;
		ti,max-div = <2>;
		reg = <0x0528>;
	};

	dmic_sync_mux_ck: dmic_sync_mux_ck {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
		ti,bit-shift = <26>;
		reg = <0x0538>;
	};

	dmic_gfclk: dmic_gfclk {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
		ti,bit-shift = <24>;
		reg = <0x0538>;
	};

	mcasp_sync_mux_ck: mcasp_sync_mux_ck {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
		ti,bit-shift = <26>;
		reg = <0x0540>;
	};

	mcasp_gfclk: mcasp_gfclk {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
		ti,bit-shift = <24>;
		reg = <0x0540>;
	};

	mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
		ti,bit-shift = <26>;
		reg = <0x0548>;
	};

	mcbsp1_gfclk: mcbsp1_gfclk {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
		ti,bit-shift = <24>;
		reg = <0x0548>;
	};

	mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
		ti,bit-shift = <26>;
		reg = <0x0550>;
	};

	mcbsp2_gfclk: mcbsp2_gfclk {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
		ti,bit-shift = <24>;
		reg = <0x0550>;
	};

	mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
		ti,bit-shift = <26>;
		reg = <0x0558>;
	};

	mcbsp3_gfclk: mcbsp3_gfclk {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
		ti,bit-shift = <24>;
		reg = <0x0558>;
	};

	timer5_gfclk_mux: timer5_gfclk_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
		ti,bit-shift = <24>;
		reg = <0x0568>;
	};

	timer6_gfclk_mux: timer6_gfclk_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
		ti,bit-shift = <24>;
		reg = <0x0570>;
	};

	timer7_gfclk_mux: timer7_gfclk_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
		ti,bit-shift = <24>;
		reg = <0x0578>;
	};

	timer8_gfclk_mux: timer8_gfclk_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
		ti,bit-shift = <24>;
		reg = <0x0580>;
	};

	dummy_ck: dummy_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};
};
&prm_clocks {
	sys_clkin: sys_clkin {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
		reg = <0x0110>;
		ti,index-starts-at-one;
	};

	abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&sys_clkin>, <&sys_32k_ck>;
		reg = <0x0108>;
	};

	abe_dpll_clk_mux: abe_dpll_clk_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&sys_clkin>, <&sys_32k_ck>;
		reg = <0x010c>;
	};

	custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&sys_clkin>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	dss_syc_gfclk_div: dss_syc_gfclk_div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&sys_clkin>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	wkupaon_iclk_mux: wkupaon_iclk_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&sys_clkin>, <&abe_lp_clk_div>;
		reg = <0x0108>;
	};

	l3instr_ts_gclk_div: l3instr_ts_gclk_div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&wkupaon_iclk_mux>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	gpio1_dbclk: gpio1_dbclk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&sys_32k_ck>;
		ti,bit-shift = <8>;
		reg = <0x1938>;
	};

	timer1_gfclk_mux: timer1_gfclk_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&sys_clkin>, <&sys_32k_ck>;
		ti,bit-shift = <24>;
		reg = <0x1940>;
	};
};
&cm_core_clocks {

	dpll_per_byp_mux: dpll_per_byp_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
		ti,bit-shift = <23>;
		reg = <0x014c>;
	};

	dpll_per_ck: dpll_per_ck {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-clock";
		clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
		reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
	};

	dpll_per_x2_ck: dpll_per_x2_ck {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-x2-clock";
		clocks = <&dpll_per_ck>;
	};
	
	dpll_per_m6x2_ck: dpll_per_m6x2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_per_x2_ck>;
		ti,max-div = <31>;
		ti,autoidle-shift = <8>;
		reg = <0x0160>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	dpll_per_h11x2_ck: dpll_per_h11x2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_per_x2_ck>;
		ti,max-div = <63>;
		reg = <0x0158>;
		ti,index-starts-at-one;
	};

	dpll_per_h12x2_ck: dpll_per_h12x2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_per_x2_ck>;
		ti,max-div = <63>;
		reg = <0x015c>;
		ti,index-starts-at-one;
	};

	dpll_per_h14x2_ck: dpll_per_h14x2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_per_x2_ck>;
		ti,max-div = <63>;
		reg = <0x0164>;
		ti,index-starts-at-one;
	};

	dpll_per_m2_ck: dpll_per_m2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_per_ck>;
		ti,max-div = <31>;
		reg = <0x0150>;
		ti,index-starts-at-one;
	};

	dpll_per_m2x2_ck: dpll_per_m2x2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_per_x2_ck>;
		ti,max-div = <31>;
		reg = <0x0150>;
		ti,index-starts-at-one;
	};

	dpll_per_m3x2_ck: dpll_per_m3x2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_per_x2_ck>;
		ti,max-div = <31>;
		reg = <0x0154>;
		ti,index-starts-at-one;
	};

	dpll_unipro1_ck: dpll_unipro1_ck {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-clock";
		clocks = <&sys_clkin>, <&sys_clkin>;
		reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
	};

	dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_unipro1_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll_unipro1_m2_ck: dpll_unipro1_m2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_unipro1_ck>;
		ti,max-div = <127>;
		reg = <0x0210>;
		ti,index-starts-at-one;
	};

	dpll_unipro2_ck: dpll_unipro2_ck {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-clock";
		clocks = <&sys_clkin>, <&sys_clkin>;
		reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
	};

	dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_unipro2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll_unipro2_m2_ck: dpll_unipro2_m2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_unipro2_ck>;
		ti,max-div = <127>;
		reg = <0x01d0>;
		ti,index-starts-at-one;
	};

	dpll_usb_byp_mux: dpll_usb_byp_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
		ti,bit-shift = <23>;
		reg = <0x018c>;
	};

	dpll_usb_ck: dpll_usb_ck {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-j-type-clock";
		clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
		reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
	};

	dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_usb_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll_usb_m2_ck: dpll_usb_m2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_usb_ck>;
		ti,max-div = <127>;
		reg = <0x0190>;
		ti,index-starts-at-one;
	};
	
	ducati_clk_mux_ck: ducati_clk_mux_ck {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
		reg = <0x0100>;
	};

	func_128m_clk: func_128m_clk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_per_h11x2_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	func_12m_fclk: func_12m_fclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_per_m2x2_ck>;
		clock-mult = <1>;
		clock-div = <16>;
	};

	func_24m_clk: func_24m_clk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_per_m2_ck>;
		clock-mult = <1>;
		clock-div = <4>;
	};

	func_48m_fclk: func_48m_fclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_per_m2x2_ck>;
		clock-mult = <1>;
		clock-div = <4>;
	};

	func_96m_fclk: func_96m_fclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_per_m2x2_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	l3init_60m_fclk: l3init_60m_fclk {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_usb_m2_ck>;
		reg = <0x0104>;
		ti,dividers = <1>, <8>;
	};

	dss_32khz_clk: dss_32khz_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&sys_32k_ck>;
		ti,bit-shift = <11>;
		reg = <0x1420>;
	};

	dss_48mhz_clk: dss_48mhz_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&func_48m_fclk>;
		ti,bit-shift = <9>;
		reg = <0x1420>;
	};

	dss_dss_clk: dss_dss_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&dpll_per_h12x2_ck>;
		ti,bit-shift = <8>;
		reg = <0x1420>;
		ti,set-rate-parent;
	};

	dss_sys_clk: dss_sys_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&dss_syc_gfclk_div>;
		ti,bit-shift = <10>;
		reg = <0x1420>;
	};

	gpio2_dbclk: gpio2_dbclk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&sys_32k_ck>;
		ti,bit-shift = <8>;
		reg = <0x1060>;
	};

	gpio3_dbclk: gpio3_dbclk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&sys_32k_ck>;
		ti,bit-shift = <8>;
		reg = <0x1068>;
	};

	gpio4_dbclk: gpio4_dbclk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&sys_32k_ck>;
		ti,bit-shift = <8>;
		reg = <0x1070>;
	};

	gpio5_dbclk: gpio5_dbclk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&sys_32k_ck>;
		ti,bit-shift = <8>;
		reg = <0x1078>;
	};

	gpio6_dbclk: gpio6_dbclk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&sys_32k_ck>;
		ti,bit-shift = <8>;
		reg = <0x1080>;
	};

	gpio7_dbclk: gpio7_dbclk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&sys_32k_ck>;
		ti,bit-shift = <8>;
		reg = <0x1110>;
	};

	gpio8_dbclk: gpio8_dbclk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&sys_32k_ck>;
		ti,bit-shift = <8>;
		reg = <0x1118>;
	};

	iss_ctrlclk: iss_ctrlclk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&func_96m_fclk>;
		ti,bit-shift = <8>;
		reg = <0x1320>;
	};

	lli_txphy_clk: lli_txphy_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&dpll_unipro1_clkdcoldo>;
		ti,bit-shift = <8>;
		reg = <0x0f20>;
	};

	lli_txphy_ls_clk: lli_txphy_ls_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&dpll_unipro1_m2_ck>;
		ti,bit-shift = <9>;
		reg = <0x0f20>;
	};

	mmc1_32khz_clk: mmc1_32khz_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&sys_32k_ck>;
		ti,bit-shift = <8>;
		reg = <0x1628>;
	};

	sata_ref_clk: sata_ref_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&sys_clkin>;
		ti,bit-shift = <8>;
		reg = <0x1688>;
	};

	usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&dpll_usb_m2_ck>;
		ti,bit-shift = <13>;
		reg = <0x1658>;
	};

	usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&dpll_usb_m2_ck>;
		ti,bit-shift = <14>;
		reg = <0x1658>;
	};

	usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&dpll_usb_m2_ck>;
		ti,bit-shift = <7>;
		reg = <0x1658>;
	};

	usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&l3init_60m_fclk>;
		ti,bit-shift = <11>;
		reg = <0x1658>;
	};

	usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&l3init_60m_fclk>;
		ti,bit-shift = <12>;
		reg = <0x1658>;
	};

	usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&l3init_60m_fclk>;
		ti,bit-shift = <6>;
		reg = <0x1658>;
	};

	utmi_p1_gfclk: utmi_p1_gfclk {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
		ti,bit-shift = <24>;
		reg = <0x1658>;
	};

	usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&utmi_p1_gfclk>;
		ti,bit-shift = <8>;
		reg = <0x1658>;
	};

	utmi_p2_gfclk: utmi_p2_gfclk {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
		ti,bit-shift = <25>;
		reg = <0x1658>;
	};

	usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&utmi_p2_gfclk>;
		ti,bit-shift = <9>;
		reg = <0x1658>;
	};

	usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&l3init_60m_fclk>;
		ti,bit-shift = <10>;
		reg = <0x1658>;
	};

	usb_otg_ss_refclk960m: usb_otg_ss_refclk960m {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&dpll_usb_clkdcoldo>;
		ti,bit-shift = <8>;
		reg = <0x16f0>;
	};

	usb_phy_cm_clk32k: usb_phy_cm_clk32k {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&sys_32k_ck>;
		ti,bit-shift = <8>;
		reg = <0x0640>;
	};

	usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&l3init_60m_fclk>;
		ti,bit-shift = <8>;
		reg = <0x1668>;
	};

	usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&l3init_60m_fclk>;
		ti,bit-shift = <9>;
		reg = <0x1668>;
	};

	usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&l3init_60m_fclk>;
		ti,bit-shift = <10>;
		reg = <0x1668>;
	};

	fdif_fclk: fdif_fclk {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_per_h11x2_ck>;
		ti,bit-shift = <24>;
		ti,max-div = <2>;
		reg = <0x1328>;
	};

	gpu_core_gclk_mux: gpu_core_gclk_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
		ti,bit-shift = <24>;
		reg = <0x1520>;
	};

	gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
		ti,bit-shift = <25>;
		reg = <0x1520>;
	};

	hsi_fclk: hsi_fclk {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_per_m2x2_ck>;
		ti,bit-shift = <24>;
		ti,max-div = <2>;
		reg = <0x1638>;
	};

	mmc1_fclk_mux: mmc1_fclk_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
		ti,bit-shift = <24>;
		reg = <0x1628>;
	};

	mmc1_fclk: mmc1_fclk {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&mmc1_fclk_mux>;
		ti,bit-shift = <25>;
		ti,max-div = <2>;
		reg = <0x1628>;
	};

	mmc2_fclk_mux: mmc2_fclk_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
		ti,bit-shift = <24>;
		reg = <0x1630>;
	};

	mmc2_fclk: mmc2_fclk {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&mmc2_fclk_mux>;
		ti,bit-shift = <25>;
		ti,max-div = <2>;
		reg = <0x1630>;
	};

	timer10_gfclk_mux: timer10_gfclk_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&sys_clkin>, <&sys_32k_ck>;
		ti,bit-shift = <24>;
		reg = <0x1028>;
	};

	timer11_gfclk_mux: timer11_gfclk_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&sys_clkin>, <&sys_32k_ck>;
		ti,bit-shift = <24>;
		reg = <0x1030>;
	};

	timer2_gfclk_mux: timer2_gfclk_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&sys_clkin>, <&sys_32k_ck>;
		ti,bit-shift = <24>;
		reg = <0x1038>;
	};

	timer3_gfclk_mux: timer3_gfclk_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&sys_clkin>, <&sys_32k_ck>;
		ti,bit-shift = <24>;
		reg = <0x1040>;
	};

	timer4_gfclk_mux: timer4_gfclk_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&sys_clkin>, <&sys_32k_ck>;
		ti,bit-shift = <24>;
		reg = <0x1048>;
	};

	timer9_gfclk_mux: timer9_gfclk_mux {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&sys_clkin>, <&sys_32k_ck>;
		ti,bit-shift = <24>;
		reg = <0x1050>;
	};
};

&cm_core_clockdomains {
	l3init_clkdm: l3init_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&dpll_usb_ck>;
	};
};

&scrm_clocks {
	auxclk0_src_gate_ck: auxclk0_src_gate_ck {
		#clock-cells = <0>;
		compatible = "ti,composite-no-wait-gate-clock";
		clocks = <&dpll_core_m3x2_ck>;
		ti,bit-shift = <8>;
		reg = <0x0310>;
	};

	auxclk0_src_mux_ck: auxclk0_src_mux_ck {
		#clock-cells = <0>;
		compatible = "ti,composite-mux-clock";
		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
		ti,bit-shift = <1>;
		reg = <0x0310>;
	};

	auxclk0_src_ck: auxclk0_src_ck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
	};

	auxclk0_ck: auxclk0_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&auxclk0_src_ck>;
		ti,bit-shift = <16>;
		ti,max-div = <16>;
		reg = <0x0310>;
	};

	auxclk1_src_gate_ck: auxclk1_src_gate_ck {
		#clock-cells = <0>;
		compatible = "ti,composite-no-wait-gate-clock";
		clocks = <&dpll_core_m3x2_ck>;
		ti,bit-shift = <8>;
		reg = <0x0314>;
	};

	auxclk1_src_mux_ck: auxclk1_src_mux_ck {
		#clock-cells = <0>;
		compatible = "ti,composite-mux-clock";
		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
		ti,bit-shift = <1>;
		reg = <0x0314>;
	};

	auxclk1_src_ck: auxclk1_src_ck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
	};

	auxclk1_ck: auxclk1_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&auxclk1_src_ck>;
		ti,bit-shift = <16>;
		ti,max-div = <16>;
		reg = <0x0314>;
	};

	auxclk2_src_gate_ck: auxclk2_src_gate_ck {
		#clock-cells = <0>;
		compatible = "ti,composite-no-wait-gate-clock";
		clocks = <&dpll_core_m3x2_ck>;
		ti,bit-shift = <8>;
		reg = <0x0318>;
	};

	auxclk2_src_mux_ck: auxclk2_src_mux_ck {
		#clock-cells = <0>;
		compatible = "ti,composite-mux-clock";
		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
		ti,bit-shift = <1>;
		reg = <0x0318>;
	};

	auxclk2_src_ck: auxclk2_src_ck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
	};

	auxclk2_ck: auxclk2_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&auxclk2_src_ck>;
		ti,bit-shift = <16>;
		ti,max-div = <16>;
		reg = <0x0318>;
	};

	auxclk3_src_gate_ck: auxclk3_src_gate_ck {
		#clock-cells = <0>;
		compatible = "ti,composite-no-wait-gate-clock";
		clocks = <&dpll_core_m3x2_ck>;
		ti,bit-shift = <8>;
		reg = <0x031c>;
	};

	auxclk3_src_mux_ck: auxclk3_src_mux_ck {
		#clock-cells = <0>;
		compatible = "ti,composite-mux-clock";
		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
		ti,bit-shift = <1>;
		reg = <0x031c>;
	};

	auxclk3_src_ck: auxclk3_src_ck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
	};

	auxclk3_ck: auxclk3_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&auxclk3_src_ck>;
		ti,bit-shift = <16>;
		ti,max-div = <16>;
		reg = <0x031c>;
	};

	auxclk4_src_gate_ck: auxclk4_src_gate_ck {
		#clock-cells = <0>;
		compatible = "ti,composite-no-wait-gate-clock";
		clocks = <&dpll_core_m3x2_ck>;
		ti,bit-shift = <8>;
		reg = <0x0320>;
	};

	auxclk4_src_mux_ck: auxclk4_src_mux_ck {
		#clock-cells = <0>;
		compatible = "ti,composite-mux-clock";
		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
		ti,bit-shift = <1>;
		reg = <0x0320>;
	};

	auxclk4_src_ck: auxclk4_src_ck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
	};

	auxclk4_ck: auxclk4_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&auxclk4_src_ck>;
		ti,bit-shift = <16>;
		ti,max-div = <16>;
		reg = <0x0320>;
	};

	auxclkreq0_ck: auxclkreq0_ck {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
		ti,bit-shift = <2>;
		reg = <0x0210>;
	};

	auxclkreq1_ck: auxclkreq1_ck {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
		ti,bit-shift = <2>;
		reg = <0x0214>;
	};

	auxclkreq2_ck: auxclkreq2_ck {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
		ti,bit-shift = <2>;
		reg = <0x0218>;
	};

	auxclkreq3_ck: auxclkreq3_ck {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
		ti,bit-shift = <2>;
		reg = <0x021c>;
	};
};

/*
 * OmniVision OV5640 sensor driver
 *
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */



#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/log2.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>

#include <linux/gpio.h>
#include <linux/clk.h>
#include <linux/regulator/consumer.h>

#include <media/v4l2-device.h>
#include <media/v4l2-subdev.h>
#include <media/v4l2-ctrls.h>

#include <uapi/linux/videodev2.h>
#include <uapi/linux/v4l2-mediabus.h>
#include <uapi/linux/media-bus-format.h>

#include "ov5640.h"



//#define MEDIA_ENT_T_V4L2_SUBDEV_SENSOR	0x00020001

static struct ov5640_platform_data ov5640_devtype = {
	.reg_avdd = NULL,
	.reg_dovdd = NULL,
	.pre_poweron = NULL,
	.post_poweroff = NULL
};

static struct of_device_id ov5640_dt_ids[] = {
	{ .compatible = "omnivision,ov5640",	.data = &ov5640_devtype, },
	{ }
};
MODULE_DEVICE_TABLE(of, ov5640_dt_ids);

static const struct i2c_device_id ov5640_i2c_id_table[] = {
	{ "ov5640",	(kernel_ulong_t)&ov5640_devtype, },
	{ }
};
MODULE_DEVICE_TABLE(i2c, ov5640_i2c_id_table);

struct ov5640_timing_cfg {
	u16 x_addr_start;
	u16 y_addr_start;
	u16 x_addr_end;
	u16 y_addr_end;
	u16 h_output_size;
	u16 v_output_size;
	u16 h_total_size;
	u16 v_total_size;
	u16 isp_h_offset;
	u16 isp_v_offset;
	u8 h_odd_ss_inc;
	u8 h_even_ss_inc;
	u8 v_odd_ss_inc;
	u8 v_even_ss_inc;
};

struct ov5640_clk_cfg {
	u8 sc_pll_prediv;
	u8 sc_pll_rdiv;
	u8 sc_pll_mult;
	u8 sysclk_div;
	u8 mipi_div;
};

enum ov5640_size {
	OV5640_SIZE_QVGA,
	OV5640_SIZE_VGA,
	OV5640_SIZE_720P,
	OV5640_SIZE_1080P,
	OV5640_SIZE_5MP,
	OV5640_SIZE_LAST,
};

static const struct v4l2_frmsize_discrete ov5640_frmsizes[OV5640_SIZE_LAST] = {
	{  320,  240 },
	{  640,  480 },
	{ 1280,  720 },
	{ 1920, 1080 },
	{ 2592, 1944 },
};

/* Find a frame size in an array */
static int ov5640_find_framesize(u32 width, u32 height)
{
	int i;

	for (i = 0; i < OV5640_SIZE_LAST; i++) {
		if ((ov5640_frmsizes[i].width >= width) &&
		    (ov5640_frmsizes[i].height >= height))
			break;
	}

	/* If not found, select biggest */
	if (i >= OV5640_SIZE_LAST)
		i = OV5640_SIZE_LAST - 1;

	return i;
}

struct ov5640 {
	struct v4l2_subdev subdev;
	struct media_pad pad;
	struct v4l2_mbus_framefmt format;

	const struct ov5640_platform_data *pdata;

	struct v4l2_ctrl_handler ctrls;
	struct {
		struct v4l2_ctrl *pixel_rate;
	};

	/* HW control */
	struct clk *xvclk;
	struct regulator *avdd;
	struct regulator *dovdd;

	/* System Clock config */
	struct ov5640_clk_cfg clk_cfg;

	/* GPIO controls */
	int gpio_reset;
	enum of_gpio_flags gpio_reset_flags;
	int gpio_pwdn;
	enum of_gpio_flags gpio_pwdn_flags;
};

static inline struct ov5640 *to_ov5640(struct v4l2_subdev *sd)
{
	return container_of(sd, struct ov5640, subdev);
}

/**
 * struct ov5640_reg - ov5640 register format
 * @reg: 16-bit offset to register
 * @val: 8/16/32-bit register value
 * @length: length of the register
 *
 * Define a structure for OV5640 register initialization values
 */
struct ov5640_reg {
	u16	reg;
	u8	val;
};

/* TODO: Divide this properly */
static const struct ov5640_reg configscript_common1[] = {
	{ 0x3103, 0x03 },
	{ 0x3017, 0x00 },
	{ 0x3018, 0x00 },
	{ 0x3630, 0x2e },
	{ 0x3632, 0xe2 },
	{ 0x3633, 0x23 },
	{ 0x3634, 0x44 },
	{ 0x3621, 0xe0 },
	{ 0x3704, 0xa0 },
	{ 0x3703, 0x5a },
	{ 0x3715, 0x78 },
	{ 0x3717, 0x01 },
	{ 0x370b, 0x60 },
	{ 0x3705, 0x1a },
	{ 0x3905, 0x02 },
	{ 0x3906, 0x10 },
	{ 0x3901, 0x0a },
	{ 0x3731, 0x12 },
	{ 0x3600, 0x04 },
	{ 0x3601, 0x22 },
	{ 0x471c, 0x50 },
	{ 0x3002, 0x1c },
	{ 0x3006, 0xc3 },
	{ 0x300e, 0x05 },
	{ 0x302e, 0x08 },
	{ 0x3612, 0x4b },
	{ 0x3618, 0x04 },
	{ 0x3034, 0x18 },
	{ 0x3035, 0x11 },
	{ 0x3036, 0x54 },
	{ 0x3037, 0x13 },
	{ 0x3708, 0x21 },
	{ 0x3709, 0x12 },
	{ 0x370c, 0x00 },
};

/* TODO: Divide this properly */
static const struct ov5640_reg configscript_common2[] = {
	{ 0x3a02, 0x01 },
	{ 0x3a03, 0xec },
	{ 0x3a08, 0x01 },
	{ 0x3a09, 0x27 },
	{ 0x3a0a, 0x00 },
	{ 0x3a0b, 0xf6 },
	{ 0x3a0e, 0x06 },
	{ 0x3a0d, 0x08 },
	{ 0x3a14, 0x01 },
	{ 0x3a15, 0xec },
	{ 0x4001, 0x02 },
	{ 0x4004, 0x06 },
	{ 0x460b, 0x37 },
	{ 0x4750, 0x00 },
	{ 0x4751, 0x00 },
	{ 0x4800, 0x24 },
	{ 0x5a00, 0x08 },
	{ 0x5a21, 0x00 },
	{ 0x5a24, 0x00 },
	{ 0x5000, 0x27 },
	{ 0x5001, 0x87 },
	{ 0x3820, 0x40 },
	{ 0x3821, 0x06 },
	{ 0x3824, 0x01 },
	{ 0x5481, 0x08 },
	{ 0x5482, 0x14 },
	{ 0x5483, 0x28 },
	{ 0x5484, 0x51 },
	{ 0x5485, 0x65 },
	{ 0x5486, 0x71 },
	{ 0x5487, 0x7d },
	{ 0x5488, 0x87 },
	{ 0x5489, 0x91 },
	{ 0x548a, 0x9a },
	{ 0x548b, 0xaa },
	{ 0x548c, 0xb8 },
	{ 0x548d, 0xcd },
	{ 0x548e, 0xdd },
	{ 0x548f, 0xea },
	{ 0x5490, 0x1d },
	{ 0x5381, 0x20 },
	{ 0x5382, 0x64 },
	{ 0x5383, 0x08 },
	{ 0x5384, 0x20 },
	{ 0x5385, 0x80 },
	{ 0x5386, 0xa0 },
	{ 0x5387, 0xa2 },
	{ 0x5388, 0xa0 },
	{ 0x5389, 0x02 },
	{ 0x538a, 0x01 },
	{ 0x538b, 0x98 },
	{ 0x5300, 0x08 },
	{ 0x5301, 0x30 },
	{ 0x5302, 0x10 },
	{ 0x5303, 0x00 },
	{ 0x5304, 0x08 },
	{ 0x5305, 0x30 },
	{ 0x5306, 0x08 },
	{ 0x5307, 0x16 },
	{ 0x5580, 0x00 },
	{ 0x5587, 0x00 },
	{ 0x5588, 0x00 },
	{ 0x5583, 0x40 },
	{ 0x5584, 0x10 },
	{ 0x5589, 0x10 },
	{ 0x558a, 0x00 },
	{ 0x558b, 0xf8 },
	{ 0x3a0f, 0x36 },
	{ 0x3a10, 0x2e },
	{ 0x3a1b, 0x38 },
	{ 0x3a1e, 0x2c },
	{ 0x3a11, 0x70 },
	{ 0x3a1f, 0x18 },
	{ 0x3a18, 0x00 },
	{ 0x3a19, 0xf8 },
	{ 0x3003, 0x03 },
	{ 0x3003, 0x01 },
};

static const struct ov5640_timing_cfg timing_cfg[OV5640_SIZE_LAST] = {
	[OV5640_SIZE_QVGA] = {
		.x_addr_start = 0,
		.y_addr_start = 0,
		.x_addr_end = 2623,
		.y_addr_end = 1951,
		.h_output_size = 320,
		.v_output_size = 240,
		.h_total_size = 2844,
		.v_total_size = 1968,
		.isp_h_offset = 16,
		.isp_v_offset = 6,
		.h_odd_ss_inc = 1,
		.h_even_ss_inc = 1,
		.v_odd_ss_inc = 1,
		.v_even_ss_inc = 1,
	},
	[OV5640_SIZE_VGA] = {
		.x_addr_start = 0,
		.y_addr_start = 0,
		.x_addr_end = 2623,
		.y_addr_end = 1951,
		.h_output_size = 640,
		.v_output_size = 480,
		.h_total_size = 2844,
		.v_total_size = 1968,
		.isp_h_offset = 16,
		.isp_v_offset = 6,
		.h_odd_ss_inc = 1,
		.h_even_ss_inc = 1,
		.v_odd_ss_inc = 1,
		.v_even_ss_inc = 1,
	},
	[OV5640_SIZE_720P] = {
		.x_addr_start = 336,
		.y_addr_start = 434,
		.x_addr_end = 2287,
		.y_addr_end = 1522,
		.h_output_size = 1280,
		.v_output_size = 720,
		.h_total_size = 2500,
		.v_total_size = 1120,
		.isp_h_offset = 16,
		.isp_v_offset = 4,
		.h_odd_ss_inc = 1,
		.h_even_ss_inc = 1,
		.v_odd_ss_inc = 1,
		.v_even_ss_inc = 1,
	},
	[OV5640_SIZE_1080P] = {
		.x_addr_start = 336,
		.y_addr_start = 434,
		.x_addr_end = 2287,
		.y_addr_end = 1522,
		.h_output_size = 1920,
		.v_output_size = 1080,
		.h_total_size = 2500,
		.v_total_size = 1120,
		.isp_h_offset = 16,
		.isp_v_offset = 4,
		.h_odd_ss_inc = 1,
		.h_even_ss_inc = 1,
		.v_odd_ss_inc = 1,
		.v_even_ss_inc = 1,
	},
	[OV5640_SIZE_5MP] = {
		.x_addr_start = 0,
		.y_addr_start = 0,
		.x_addr_end = 2623,
		.y_addr_end = 1951,
		.h_output_size = 2592,
		.v_output_size = 1944,
		.h_total_size = 2844,
		.v_total_size = 1968,
		.isp_h_offset = 16,
		.isp_v_offset = 6,
		.h_odd_ss_inc = 1,
		.h_even_ss_inc = 1,
		.v_odd_ss_inc = 1,
		.v_even_ss_inc = 1,
	},
};

/**
 * ov5640_reg_read - Read a value from a register in an ov5640 sensor device
 * @client: i2c driver client structure
 * @reg: register address / offset
 * @val: stores the value that gets read
 *
 * Read a value from a register in an ov5640 sensor device.
 * The value is returned in 'val'.
 * Returns zero if successful, or non-zero otherwise.
 */
static int ov5640_reg_read(struct i2c_client *client, u16 reg, u8 *val)
{
	int ret;
	u8 data[2] = {0};
	struct i2c_msg msg = {
		.addr	= client->addr,
		.flags	= 0,
		.len	= 2,
		.buf	= data,
	};

	data[0] = (u8)(reg >> 8);
	data[1] = (u8)(reg & 0xff);

	ret = i2c_transfer(client->adapter, &msg, 1);
	if (ret < 0)
		goto err;

	msg.flags = I2C_M_RD;
	msg.len = 1;
	ret = i2c_transfer(client->adapter, &msg, 1);
	if (ret < 0)
		goto err;

	*val = data[0];
	return 0;

err:
	dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
	return ret;
}

/**
 * Write a value to a register in ov5640 sensor device.
 * @client: i2c driver client structure.
 * @reg: Address of the register to read value from.
 * @val: Value to be written to a specific register.
 * Returns zero if successful, or non-zero otherwise.
 */
static int ov5640_reg_write(struct i2c_client *client, u16 reg, u8 val)
{
	int ret;
	unsigned char data[3] = { (u8)(reg >> 8), (u8)(reg & 0xff), val };
	struct i2c_msg msg = {
		.addr	= client->addr,
		.flags	= 0,
		.len	= 3,
		.buf	= data,
	};

	ret = i2c_transfer(client->adapter, &msg, 1);
	if (ret < 0) {
		dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
		return ret;
	}

	return 0;
}

/**
 * Initialize a list of ov5640 registers.
 * The list of registers is terminated by the pair of values
 * @client: i2c driver client structure.
 * @reglist[]: List of address of the registers to write data.
 * Returns zero if successful, or non-zero otherwise.
 */
static int ov5640_reg_writes(struct i2c_client *client,
			     const struct ov5640_reg reglist[],
			     int size)
{
	int err = 0, i;

	for (i = 0; i < size; i++) {
		err = ov5640_reg_write(client, reglist[i].reg,
				reglist[i].val);
		if (err)
			return err;
	}
	return 0;
}

static int ov5640_reg_set(struct i2c_client *client, u16 reg, u8 val)
{
	int ret;
	u8 tmpval = 0;

	ret = ov5640_reg_read(client, reg, &tmpval);
	if (ret)
		return ret;

	return ov5640_reg_write(client, reg, tmpval | val);
}

static int ov5640_reg_clr(struct i2c_client *client, u16 reg, u8 val)
{
	int ret;
	u8 tmpval = 0;

	ret = ov5640_reg_read(client, reg, &tmpval);
	if (ret)
		return ret;

	return ov5640_reg_write(client, reg, tmpval & ~val);
}

static unsigned long ov5640_get_pclk(struct v4l2_subdev *sd)
{
	struct ov5640 *ov5640 = to_ov5640(sd);
	unsigned long xvclk, vco, mipi_pclk;

	xvclk = clk_get_rate(ov5640->xvclk);

	vco = (xvclk / ov5640->clk_cfg.sc_pll_prediv) *
		ov5640->clk_cfg.sc_pll_mult;

	mipi_pclk = vco /
		ov5640->clk_cfg.sysclk_div /
		ov5640->clk_cfg.mipi_div;

	return mipi_pclk;
}

static int ov5640_config_timing(struct v4l2_subdev *sd)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);
	struct ov5640 *ov5640 = to_ov5640(sd);
	int ret, i;

	i = ov5640_find_framesize(ov5640->format.width, ov5640->format.height);

	ret = ov5640_reg_write(client,
			0x3800,
			(timing_cfg[i].x_addr_start & 0xFF00) >> 8);
	if (ret)
		return ret;

	ret = ov5640_reg_write(client,
			0x3801,
			timing_cfg[i].x_addr_start & 0xFF);
	if (ret)
		return ret;

	ret = ov5640_reg_write(client,
			0x3802,
			(timing_cfg[i].y_addr_start & 0xFF00) >> 8);
	if (ret)
		return ret;

	ret = ov5640_reg_write(client,
			0x3803,
			timing_cfg[i].y_addr_start & 0xFF);
	if (ret)
		return ret;

	ret = ov5640_reg_write(client,
			0x3804,
			(timing_cfg[i].x_addr_end & 0xFF00) >> 8);
	if (ret)
		return ret;

	ret = ov5640_reg_write(client,
			0x3805,
			timing_cfg[i].x_addr_end & 0xFF);
	if (ret)
		return ret;

	ret = ov5640_reg_write(client,
			0x3806,
			(timing_cfg[i].y_addr_end & 0xFF00) >> 8);
	if (ret)
		return ret;

	ret = ov5640_reg_write(client,
			0x3807,
			timing_cfg[i].y_addr_end & 0xFF);
	if (ret)
		return ret;

	ret = ov5640_reg_write(client,
			0x3808,
			(timing_cfg[i].h_output_size & 0xFF00) >> 8);
	if (ret)
		return ret;

	ret = ov5640_reg_write(client,
			0x3809,
			timing_cfg[i].h_output_size & 0xFF);
	if (ret)
		return ret;

	ret = ov5640_reg_write(client,
			0x380A,
			(timing_cfg[i].v_output_size & 0xFF00) >> 8);
	if (ret)
		return ret;

	ret = ov5640_reg_write(client,
			0x380B,
			timing_cfg[i].v_output_size & 0xFF);
	if (ret)
		return ret;

	ret = ov5640_reg_write(client,
			0x380C,
			(timing_cfg[i].h_total_size & 0xFF00) >> 8);
	if (ret)
		return ret;

	ret = ov5640_reg_write(client,
			0x380D,
			timing_cfg[i].h_total_size & 0xFF);
	if (ret)
		return ret;

	ret = ov5640_reg_write(client,
			0x380E,
			(timing_cfg[i].v_total_size & 0xFF00) >> 8);
	if (ret)
		return ret;

	ret = ov5640_reg_write(client,
			0x380F,
			timing_cfg[i].v_total_size & 0xFF);
	if (ret)
		return ret;

	ret = ov5640_reg_write(client,
			0x3810,
			(timing_cfg[i].isp_h_offset & 0xFF00) >> 8);
	if (ret)
		return ret;

	ret = ov5640_reg_write(client,
			0x3811,
			timing_cfg[i].isp_h_offset & 0xFF);
	if (ret)
		return ret;

	ret = ov5640_reg_write(client,
			0x3812,
			(timing_cfg[i].isp_v_offset & 0xFF00) >> 8);
	if (ret)
		return ret;

	ret = ov5640_reg_write(client,
			0x3813,
			timing_cfg[i].isp_v_offset & 0xFF);
	if (ret)
		return ret;

	ret = ov5640_reg_write(client,
			0x3814,
			((timing_cfg[i].h_odd_ss_inc & 0xF) << 4) |
			(timing_cfg[i].h_even_ss_inc & 0xF));
	if (ret)
		return ret;

	ret = ov5640_reg_write(client,
			0x3815,
			((timing_cfg[i].v_odd_ss_inc & 0xF) << 4) |
			(timing_cfg[i].v_even_ss_inc & 0xF));

	return ret;
}

static struct v4l2_mbus_framefmt *
__ov5640_get_pad_format(struct ov5640 *ov5640, struct v4l2_subdev_pad_config *cfg,
			 unsigned int pad, enum v4l2_subdev_format_whence which)
{
	switch (which) {
	case V4L2_SUBDEV_FORMAT_TRY:
		return v4l2_subdev_get_try_format(&ov5640->subdev, cfg, pad);
	case V4L2_SUBDEV_FORMAT_ACTIVE:
		return &ov5640->format;
	default:
		return NULL;
	}
}

/* -----------------------------------------------------------------------------
 * V4L2 subdev internal operations
 */

static int ov5640_s_power(struct v4l2_subdev *sd, int on)
{
	int ret;

	struct ov5640 *ov5640 = to_ov5640(sd);
	struct i2c_client *client = v4l2_get_subdevdata(sd);
	struct device *dev = &client->dev;

	if (on) {

		if (ov5640->pdata->pre_poweron) {
			ret = ov5640->pdata->pre_poweron(sd);
			if (ret) {
				dev_err(dev,
					"Error in pre_poweron (%d)\n", ret);
				goto err_pwr_on;
			}
		}

		if (ov5640->dovdd) {
			ret = regulator_enable(ov5640->dovdd);
			if (ret) {
				dev_err(dev,
					"Error in enabling DOVDD (%d)\n", ret);
				goto err_dvdd_en;
			}
		}

		if (ov5640->avdd) {
			ret = regulator_enable(ov5640->avdd);
			if (ret) {
				dev_err(dev,
					"Error in enabling AVDD (%d)\n", ret);
				goto err_avdd_en;
			}
			usleep_range(5000, 5000);
		}

		ret = clk_prepare(ov5640->xvclk);
		if (ret) {
			dev_err(dev, "Error in preparing XVCLK (%d)\n", ret);
			goto err_clk_preen;
		}

		ret = clk_enable(ov5640->xvclk);
		if (ret) {
			dev_err(dev, "Error in enabling XVCLK (%d)\n", ret);
			goto err_clk_preen;
		}

		if (gpio_is_valid(ov5640->gpio_pwdn)) {
			gpio_set_value(ov5640->gpio_pwdn,
				       ov5640->gpio_pwdn_flags & OF_GPIO_ACTIVE_LOW ?
				       1 : 0);
		}
		usleep_range(2000, 2000);
	} else {
		if (gpio_is_valid(ov5640->gpio_pwdn)) {
			gpio_set_value(ov5640->gpio_pwdn,
				       ov5640->gpio_pwdn_flags & OF_GPIO_ACTIVE_LOW ?
				       0 : 1);
		}
		clk_disable(ov5640->xvclk);
		clk_unprepare(ov5640->xvclk);
		if (ov5640->avdd)
			regulator_disable(ov5640->avdd);
		if (ov5640->dovdd)
			regulator_disable(ov5640->dovdd);
		if (ov5640->pdata->post_poweroff)
			ov5640->pdata->post_poweroff(sd);
	}

	return 0;

 err_clk_preen:
	if (ov5640->avdd)
		regulator_disable(ov5640->avdd);
 err_avdd_en:
	if (ov5640->dovdd)
		regulator_disable(ov5640->dovdd);
 err_dvdd_en:
	if (ov5640->pdata->post_poweroff)
		ov5640->pdata->post_poweroff(sd);
 err_pwr_on:
	return ret;
}

static struct v4l2_subdev_core_ops ov5640_subdev_core_ops = {
	.s_power	= ov5640_s_power,
/*
	.s_ctrl = ov5640_s_ctrl (V4L2_CID_AUTO_FOCUS_START)
*/
};

static int ov5640_g_fmt(struct v4l2_subdev *sd,
			struct v4l2_subdev_pad_config *cfg,
			struct v4l2_subdev_format *format)
{
	struct ov5640 *ov5640 = to_ov5640(sd);

	format->format = *__ov5640_get_pad_format(ov5640, cfg, format->pad,
						   format->which);

	return 0;
}

static int ov5640_s_fmt(struct v4l2_subdev *sd,
			struct v4l2_subdev_pad_config *cfg,
			struct v4l2_subdev_format *format)
{
	struct ov5640 *ov5640 = to_ov5640(sd);
	struct v4l2_mbus_framefmt *__format;

	__format = __ov5640_get_pad_format(ov5640, cfg, format->pad,
					    format->which);

	*__format = format->format;

	/* changed: val64 was deprecated */
	ov5640->pixel_rate->cur.val = ov5640_get_pclk(sd) / 16;

	return 0;
}

static int ov5640_enum_fmt(struct v4l2_subdev *subdev,
			   struct v4l2_subdev_pad_config *cfg,
			   struct v4l2_subdev_mbus_code_enum *code)
{
	if (code->index >= 2)
		return -EINVAL;

	switch (code->index) {
	case 0:
		code->code = MEDIA_BUS_FMT_UYVY8_1X16;
		break;
	case 1:
		code->code = MEDIA_BUS_FMT_YUYV8_1X16;
		break;
	}
	return 0;
}

static int ov5640_enum_framesizes(struct v4l2_subdev *subdev,
				   struct v4l2_subdev_pad_config *cfg,
				   struct v4l2_subdev_frame_size_enum *fse)
{
	if ((fse->index >= OV5640_SIZE_LAST) ||
	    (fse->code != MEDIA_BUS_FMT_UYVY8_1X16 &&
	     fse->code != MEDIA_BUS_FMT_YUYV8_1X16))
		return -EINVAL;

	fse->min_width = ov5640_frmsizes[fse->index].width;
	fse->max_width = fse->min_width;
	fse->min_height = ov5640_frmsizes[fse->index].height;
	fse->max_height = fse->min_height;

	return 0;
}

static int ov5640_s_stream(struct v4l2_subdev *sd, int enable)
{
	struct ov5640 *ov5640 = to_ov5640(sd);
	struct i2c_client *client = v4l2_get_subdevdata(sd);
	int ret = 0;

	if (enable) {
		u8 fmtreg = 0, fmtmuxreg = 0;
		int i;

		switch ((u32)ov5640->format.code) {
		case MEDIA_BUS_FMT_UYVY8_1X16:
			fmtreg = 0x32;
			fmtmuxreg = 0;
			break;
		case MEDIA_BUS_FMT_YUYV8_1X16:
			fmtreg = 0x30;
			fmtmuxreg = 0;
			break;
		default:
			/* This shouldn't happen */
			ret = -EINVAL;
			return ret;
		}

		ret = ov5640_reg_write(client, 0x4300, fmtreg);
		if (ret)
			return ret;

		ret = ov5640_reg_write(client, 0x501F, fmtmuxreg);
		if (ret)
			return ret;

		ret = ov5640_config_timing(sd);
		if (ret)
			return ret;

		i = ov5640_find_framesize(ov5640->format.width, ov5640->format.height);
		if ((i == OV5640_SIZE_QVGA) ||
		    (i == OV5640_SIZE_VGA) ||
		    (i == OV5640_SIZE_720P)) {
			ret = ov5640_reg_write(client, 0x3108,
					(i == OV5640_SIZE_720P) ? 0x1 : 0);
			if (ret)
				return ret;
			ret = ov5640_reg_set(client, 0x5001, 0x20);
		} else {
			ret = ov5640_reg_clr(client, 0x5001, 0x20);
			if (ret)
				return ret;
			ret = ov5640_reg_write(client, 0x3108, 0x2);
		}

		/* bring ov5640 out of power down mode */
		ret = ov5640_reg_clr(client, 0x3008, 0x40);
		if (ret)
			goto out;
	} else {
		u8 tmpreg = 0;

		ret = ov5640_reg_read(client, 0x3008, &tmpreg);
		if (ret)
			goto out;

		ret = ov5640_reg_write(client, 0x3008, tmpreg | 0x40);
		if (ret)
			goto out;
	}

out:
	return ret;
}

static struct v4l2_subdev_video_ops ov5640_subdev_video_ops = {
	.s_stream	= ov5640_s_stream,
};

static struct v4l2_subdev_pad_ops ov5640_subdev_pad_ops = {
	.enum_mbus_code = ov5640_enum_fmt,
	.enum_frame_size = ov5640_enum_framesizes,
	.get_fmt = ov5640_g_fmt,
	.set_fmt = ov5640_s_fmt,
};

static int ov5640_g_skip_frames(struct v4l2_subdev *sd, u32 *frames)
{
	/* Quantity of initial bad frames to skip. Revisit. */
	*frames = 3;

	return 0;
}

static struct v4l2_subdev_sensor_ops ov5640_subdev_sensor_ops = {
	.g_skip_frames	= ov5640_g_skip_frames,
};

static struct v4l2_subdev_ops ov5640_subdev_ops = {
	.core	= &ov5640_subdev_core_ops,
	.video	= &ov5640_subdev_video_ops,
	.pad	= &ov5640_subdev_pad_ops,
	.sensor	= &ov5640_subdev_sensor_ops,
};

static int ov5640_registered(struct v4l2_subdev *subdev)
{
	struct i2c_client *client = v4l2_get_subdevdata(subdev);
	struct ov5640 *ov5640 = to_ov5640(subdev);
	int ret = 0;
	u8 revision = 0;

	ret = ov5640_s_power(subdev, 1);
	if (ret < 0) {
		dev_err(&client->dev, "OV5640 power up failed\n");
		return ret;
	}

	ret = ov5640_reg_read(client, 0x302A, &revision);
	if (ret) {
		dev_err(&client->dev, "Failure to detect OV5640 chip\n");
		goto out;
	}

	revision &= 0xF;

	dev_info(&client->dev, "Detected a OV5640 chip, revision %x\n",
		 revision);

	/* SW Reset */
	ret = ov5640_reg_set(client, 0x3008, 0x80);
	if (ret)
		goto out;
	
	msleep(2);

	ret = ov5640_reg_clr(client, 0x3008, 0x80);
	if (ret)
		goto out;

	
	/* SW Powerdown */
	ret = ov5640_reg_set(client, 0x3008, 0x40);
	if (ret)
		goto out;

	
	
	ret = ov5640_reg_writes(client, configscript_common1,
			ARRAY_SIZE(configscript_common1));
	if (ret)
		goto out;
		

	ret = ov5640_reg_writes(client, configscript_common2,
			ARRAY_SIZE(configscript_common2));

	if (ret)
		goto out;
		

	/* Init controls */
	ret = v4l2_ctrl_handler_init(&ov5640->ctrls, 1);
	if (ret)
		goto out;
		

	ov5640->pixel_rate = v4l2_ctrl_new_std(&ov5640->ctrls,
					       NULL,
					       V4L2_CID_PIXEL_RATE,
					       1, INT_MAX, 1,
					       ov5640_get_pclk(subdev) / 16);
	subdev->ctrl_handler = &ov5640->ctrls;
	
	dev_info(&client->dev, "ov5640_registered complete \n");
out:
	ov5640_s_power(subdev, 0);

	return ret;
}

static int ov5640_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
{
	struct v4l2_mbus_framefmt *format;

	format = v4l2_subdev_get_try_format(subdev, fh->pad, 0);
	format->code = MEDIA_BUS_FMT_UYVY8_1X16;
	format->width = ov5640_frmsizes[OV5640_SIZE_VGA].width;
	format->height = ov5640_frmsizes[OV5640_SIZE_VGA].height;
	format->field = V4L2_FIELD_NONE;
	format->colorspace = V4L2_COLORSPACE_JPEG;

	return 0;
}

static int ov5640_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
{
	return 0;
}

static struct v4l2_subdev_internal_ops ov5640_subdev_internal_ops = {
	.registered = ov5640_registered,
	.open = ov5640_open,
	.close = ov5640_close,
};

static int ov5640_get_resources(struct ov5640 *ov5640, struct device *dev)
{
	const struct ov5640_platform_data *pdata = ov5640->pdata;
	int ret = 0;

	ov5640->xvclk = of_clk_get(dev->of_node, 0);
	if (IS_ERR(ov5640->xvclk)) {
		dev_err(dev, "Unable to get XVCLK\n");
		return -ENODEV;
	}

	if (clk_round_rate(ov5640->xvclk, 24000000) != 24000000)
		dev_warn(dev, "XVCLK set to rounded aproximate (%lu Hz)\n",
			 clk_round_rate(ov5640->xvclk, 24000000));

	if (clk_set_rate(ov5640->xvclk,
			 clk_round_rate(ov5640->xvclk, 24000000))) {
		dev_err(dev, "Unable to change XVCLK rate!\n");
		ret = -EINVAL;
		goto err_clk_set_rate;
	}

	if (!pdata->reg_avdd)
		goto get_reg_dovdd;

	ov5640->avdd = devm_regulator_get(dev, "avdd");
	if (IS_ERR(ov5640->avdd)) {
		dev_err(dev, "Unable to get AVDD (%s) regulator\n",
			pdata->reg_avdd);
		ret = -ENODEV;
		goto err_reg_avdd;
	}

	if (regulator_set_voltage(ov5640->avdd, 2800000, 2800000)) {
		dev_err(dev, "Unable to set valid AVDD (%s) regulator"
			" voltage to: 2.8V\n", pdata->reg_avdd);
		ret = -ENODEV;
		goto err_reg_avdd;
	}

get_reg_dovdd:
	if (!pdata->reg_dovdd)
		goto get_gpio_pwdn;

	ov5640->dovdd = devm_regulator_get(dev, "dvdd");
	if (IS_ERR(ov5640->dovdd)) {
		dev_err(dev, "Unable to get DOVDD (%s) regulator\n",
			pdata->reg_dovdd);
		ret = -ENODEV;
		goto err_reg_dovdd;
	}

	if (regulator_set_voltage(ov5640->dovdd, 1800000, 1800000)) {
		dev_err(dev, "Unable to set valid DOVDD (%s) regulator"
			" voltage to: 1.8V\n", pdata->reg_dovdd);
		ret = -ENODEV;
		goto err_reg_dovdd;
	}

get_gpio_pwdn:
	ov5640->gpio_pwdn = of_get_named_gpio_flags(dev->of_node,
						    "pwdn-gpios",
						    0,
						    &ov5640->gpio_pwdn_flags);
	if (!gpio_is_valid(ov5640->gpio_pwdn))
		goto get_gpio_resetb;

	if (gpio_request_one(ov5640->gpio_pwdn,
			     ov5640->gpio_pwdn_flags & OF_GPIO_ACTIVE_LOW ?
			     GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH,
			     "OV5640_PWDN")) {
		dev_err(dev, "Cannot request GPIO %d for power down\n", ov5640->gpio_pwdn);
		ret = -ENODEV;
		goto err_gpio_pwdn;
	}

get_gpio_resetb:
	ov5640->gpio_reset = of_get_named_gpio_flags(dev->of_node,
						     "reset-gpios",
						     0,
						     &ov5640->gpio_reset_flags);
	if (!gpio_is_valid(ov5640->gpio_reset))
		goto out;

	if (gpio_request_one(ov5640->gpio_reset,
			     ov5640->gpio_reset_flags & OF_GPIO_ACTIVE_LOW  ?
			     GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
			     "OV5640_RESETB")) {
		dev_err(dev, "Cannot request GPIO %d for reset\n", ov5640->gpio_reset);
		ret = -ENODEV;
		goto err_gpio_resetb;
	}

out:
	dev_err(dev, "Got GPIOs {reset = %d, power down = %d}\n", ov5640->gpio_reset, ov5640->gpio_pwdn);
	return 0;

err_gpio_resetb:
	if (gpio_is_valid(ov5640->gpio_pwdn))
		gpio_free(ov5640->gpio_pwdn);
err_gpio_pwdn:
err_reg_dovdd:
err_reg_avdd:
err_clk_set_rate:
	clk_put(ov5640->xvclk);

	return ret;
}

static void ov5640_put_resources(struct ov5640 *ov5640)
{
	if (gpio_is_valid(ov5640->gpio_reset))
		gpio_free(ov5640->gpio_reset);
	if (gpio_is_valid(ov5640->gpio_pwdn))
		gpio_free(ov5640->gpio_pwdn);
	clk_put(ov5640->xvclk);
}

static int ov5640_probe(struct i2c_client *i2c,
			 const struct i2c_device_id *id)
{
	struct ov5640 *ov5640;
	int ret;
	const struct of_device_id *of_device_id = NULL;
	
	dev_info(&i2c->dev, "ov5640_probe 1 \n");

	if (i2c->dev.of_node) {
		of_device_id = of_match_device(ov5640_dt_ids, &i2c->dev);
	}

	if (of_device_id == NULL) {
		dev_err(&i2c->dev, "Device not found in DT!\n");
		return -ENODEV;
	}

	dev_info(&i2c->dev, "ov5640_probe 2 \n");


	ov5640 = kzalloc(sizeof(*ov5640), GFP_KERNEL);
	if (!ov5640)
		return -ENOMEM;

	/* for regulators and pre/post power functions */
	ov5640->pdata = (struct ov5640_platform_data *)id->driver_data;

	ret = ov5640_get_resources(ov5640, &i2c->dev);
	if (ret) {
		kfree(ov5640);
		return ret;
	}

	dev_info(&i2c->dev, "ov5640_probe 3 \n");

	ov5640->format.code = MEDIA_BUS_FMT_UYVY8_1X16;
	ov5640->format.width = ov5640_frmsizes[OV5640_SIZE_VGA].width;
	ov5640->format.height = ov5640_frmsizes[OV5640_SIZE_VGA].height;
	ov5640->format.field = V4L2_FIELD_NONE;
	ov5640->format.colorspace = V4L2_COLORSPACE_JPEG;

	ov5640->clk_cfg.sc_pll_prediv = 3;
	ov5640->clk_cfg.sc_pll_rdiv = 1;
	ov5640->clk_cfg.sc_pll_mult = 84;
	ov5640->clk_cfg.sysclk_div = 1;
	ov5640->clk_cfg.mipi_div = 1;

	dev_info(&i2c->dev, "ov5640_probe 4 \n");

	v4l2_i2c_subdev_init(&ov5640->subdev, i2c, &ov5640_subdev_ops);
	ov5640->subdev.internal_ops = &ov5640_subdev_internal_ops;
	ov5640->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
	ov5640->subdev.entity.type = MEDIA_ENT_T_V4L2_SUBDEV_SENSOR;

	ov5640->pad.flags = MEDIA_PAD_FL_SOURCE;
	ret = media_entity_init(&ov5640->subdev.entity, 1, (void *) &ov5640->pad, 0);
	
	//~ v4l2_i2c_subdev_init(&ov5640->subdev, i2c, &ov5640_subdev_ops);
	//~ ov5640->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
	//~ ov5640->subdev.internal_ops = &ov5640_subdev_internal_ops;
	//~ ov5640->subdev.dev = &i2c->dev;
	//~ ov5640->pad.flags = MEDIA_PAD_FL_SOURCE;
	//~ ov5640->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
	//~ 
	//~ ret = media_entity_pads_init(&ov5640->subdev.entity, 1,(void *) &ov5640->pad);
	
	dev_info(&i2c->dev, "ov5640_probe 5 \n");

	
	if (ret < 0)
		goto err;

	dev_info(&i2c->dev, "ov5640_probe 6 \n");

	ov5640->subdev.dev = &i2c->dev;
	ret = v4l2_async_register_subdev(&ov5640->subdev);
	if (ret < 0)
		goto err;

	dev_info(&i2c->dev, "ov5640_probe 7 \n");

	return 0;
err:
	media_entity_cleanup(&ov5640->subdev.entity);
	ov5640_put_resources(ov5640);
	kfree(ov5640);
	return ret;
}

static int ov5640_remove(struct i2c_client *i2c)
{
	struct v4l2_subdev *subdev = i2c_get_clientdata(i2c);
	struct ov5640 *ov5640 = to_ov5640(subdev);

	v4l2_async_unregister_subdev(subdev);
	v4l2_ctrl_handler_free(&ov5640->ctrls);
	media_entity_cleanup(&subdev->entity);
	v4l2_device_unregister_subdev(subdev);
	ov5640_put_resources(ov5640);
	kfree(ov5640);
	return 0;
}

static struct i2c_driver ov5640_i2c_driver = {
	.driver = {
		.name 		= "ov5640",
		.owner		= THIS_MODULE,
		.of_match_table = of_match_ptr(ov5640_dt_ids),
	},
	.probe		= ov5640_probe,
	.remove		= ov5640_remove,
	.id_table	= ov5640_i2c_id_table,
};

module_i2c_driver(ov5640_i2c_driver);

MODULE_ALIAS("i2c:ov5640");
MODULE_DESCRIPTION("OmniVision OV5640 Camera driver");
MODULE_AUTHOR("Sergio Aguirre <saaguirre@ti.com>");
MODULE_LICENSE("GPL v2");