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Hi everyone,
I am currently doing some preparatory work for a memory unit testing design and we plan to use the TLK2711-SP in combination with an Xilinx Spartan 6 FPGA. For providing the reference clock to the TLK2711-SP we have two possibilities:
1) Direct connection of a Silicon Labs Si570 I2C Programmable XO Oscillator to the TLK2711-SP reference clock input.
Si570 --> TLK2711-SP
2) Connection of Silicon Labs Si570 I2C Programmable XO Oscillator to the Spartan 6 (internal Delay Locked Loop) and output to two TLK2711-SP.
Si570 --> Spartan 6 (DLL) ----> TLK2711-SP
|
--> TLK2711-SP
The reference clock timing requirements stated in the data sheet TLK2711-SP say: "Jitter: peak to peak max. 40 ps". Now my question is what type of jitter is this? Is it period jitter, cycle-to-cylce jitter or time interval error? And what part of the jitter is included in this value? Is it 40ps of periodic jitter + random jitter?
best regards,
Florian