ISO7341C: layout considerations

Hi Asaf,

Thank you for posting to E2E! Since routing traces, vias, or copper planes underneath isolation devices can compromise the isolation barrier, we normally do not recommend it. Depending on the functional isolation requirements of your system, this may be okay, so please ensure to test the isolation performance accordingly.

Regarding device functionality, the ISO7341C should operate normally without any problems or changes in device-level performance whether signals are routed underneath it or not. The electrical, timing, and isolation specs of the device will remain the same, however the system itself may have reduced isolation performance because of the reduced width of the isolation barrier (also known as creepage/clearance).

The isolation specs of the isolator apply to the system when the isolator is the shortest path across the isolation barrier measured from pins on one side of the device to pins on the other side, specified by the CLR and CPG specs in its datasheet. When signals, vias, or planes shorten the distance across the isolation barrier from these values, the maximum isolation voltage ratings may decrease, especially if copper is exposed on the top or bottom surfaces of the PCB. The amount the isolation performance changes by varies based on the isolation parameter in question, the industry standard specifying the rating, and the shortest distance between conductive materials in the isolation barrier.

I hope this answers your questions.


Respectfully,
Manuel Chavez