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Hi team,
Could you please review this part on the schematic? It is on page 4, U3.
One thing that looks strange to me is I believe this can only provide a 3.3V or 5V isolated rail. However, the LDO (U4) slightly downstream provides a 5.2V rail. This seems odd to me.
Can you let me know if I'm correct about the SN65x providing the 3.3V or 5V rail, and if you see any issues with this implementation?
Thanks,
Lauren
Hi Lauren,
Thank you for sharing the schematic for review.
Please find my inputs below, thanks.
Regards,
Koteshwar Rao
Thank you Koteshwar.
Can you explain why you recommend decreasing the capacitance on VCC pin? Section 8.2.2.4 on the datasheet says that capacitance should be between 1uF-100uF, it's at 2uF right now with the two 1uF caps.
The LDO drop out is 250mV at 200mA. Let me know if you think that is enough. I will also ask the LDO team to review because this is supposed to be fixed at 5V but it is listed as supplying 5.2V.
Thanks,
Lauren
Hi Lauren,
Thanks for your inputs.
Can you explain why you recommend decreasing the capacitance on VCC pin? Section 8.2.2.4 on the datasheet says that capacitance should be between 1uF-100uF, it's at 2uF right now with the two 1uF caps.
I am not suggesting to decrease rather I am asking you to introduce one 0.1µF capacitor either adding a new one or replacing one of the existing capacitors. Most power supplies and/or digital circuits typically require one bulk cap and one transient / decoupling cap. The 1µF cap serves as a bulk cap whose value can be anywhere between 1µF to 100µF while the 0.1µF serves as the decoupling cap.
The LDO drop out is 250mV at 200mA. Let me know if you think that is enough. I will also ask the LDO team to review because this is supposed to be fixed at 5V but it is listed as supplying 5.2V.
Yes, 250mV sounds good. The LDO team will be able to suggest the best device for this requirement. Thanks.
Regards,
Koteshwar Rao