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ISO1042: CAN bit rate vs RC decay

Part Number: ISO1042

Hi,

A follow up on the thread that discussed the max CAN bitrate versus the Recessive bit RC decay:

We are considering a protective network at each CAN node consisting av a simple bidirectional TVS from both CAN_H and CAN_L to the local ground at each node. Now some questions:

- Since both TVS diodes are connected to the same point (the local ground) the bus capacitance between CAN_H and CAN_L will be the sum of two TVS diodes. Is this correct ?

- When calculating the RC decay time when several nodes are connected to the CAN bus: should I sum up the parallel capacitance of the TVS diodes on all nodes, or should I only consider the local capacitance on a single node when calculating the worst case RC decay time ?
Basically I wonder if the RC decay time is affacted when more nodes are connected to the CAN bus.

  • Hi again,

    An additional question:

    - What is the maximum portion for the RC decay time during a recessive bit (logic "1") period ? 
      Basically I wonder how much minimum time is needed by the transceiver to be able to sample/interpret the logic level in a correct and stable way. 

  • Hello again Ronny, 

    - Since both TVS diodes are connected to the same point (the local ground) the bus capacitance between CAN_H and CAN_L will be the sum of two TVS diodes. Is this correct ?

    You are close, you will add the capacitance of the TVS diodes as capacitors in series since the two TVS diodes are connected through the GND node C_total = 1/(1/C +1/C). 

    - When calculating the RC decay time when several nodes are connected to the CAN bus: should I sum up the parallel capacitance of the TVS diodes on all nodes, or should I only consider the local capacitance on a single node when calculating the worst case RC decay time ?

    Yes, RC decay times will be affected when more nodes are added because of the increased capacitive load. I would recommend calculating the total capacitance of the bus by 1st calculating the maximum capacitance of a single node (including TVS and device capacitance) and then multiply by the number of nodes.

    - What is the maximum portion for the RC decay time during a recessive bit (logic "1") period ? 

    The best practice is to only allow decay up to 75% of the bit width, where bit width is the pulse width of a single bit. This is covered in detail in the content provide in the other post ((+) ISO1042: Max load capacitance vs rise/fall times - Isolation forum - Isolation - TI E2E support forums)

    Best,
    Andrew

  • OK, great, thanks!