ISO1211: broken wire detection

Andraas thank you for opening this discussion thread.

I would like to provide additional details about our application.
We intend to use this chip for input diagnostics. Specifically, a 100 Hz signal with 50 µs pulses is planned for diagnostics purposes.

I have reviewed the following documentation:

ISO121x Isolated 24-V to 60-V Digital Input Receivers for Digital Input Modules datasheet (Rev. F)

ISO1211 Isolated Digital-Input Receiver Evaluation Module (Rev. A)

How to implement wire‐break detection and diagnostics in isolated digital inputs (Rev. A)

Broken Wire Detection Using an Optical Switch Reference Design

TIDA-01509 Schematic and Block Diagram

I have several technical questions:

1. What is the expected propagation delay (min, max)?
   Does it depend on the input voltage?

2. How can C_HOLD be determined?

3. Is the purpose of the SUB pin solely for heat dissipation?
   Why should not be connected to FGND?
   Why is a resistor connection between the SUB pin and FGND foreseen in the ISO1211EVM documentation?

I modified the ISO1211EVM by adding an optocoupler in series with FGND. However, Case2, as shown in the diagram, does function within the limited range of 8.7V to 9.2V.
This relatively narrow range results in false detection of broken wires. Is this behavior expected?

I would greatly appreciate any clarification on these points.

Hi Gorazd,

Thank you for going through all the useful resources. Please see my answers listed below, thanks.

1. The propagation delay in going to be according what is listed in the datasheet as t_PLH. This does have dependency on input voltage and our data in datasheet is for 18V. We don't have data for other voltages but we expect the change to be minimal.
2. Since C_HOLD is not a requirement of ISO121x for operation, it doesn't have a defined value.
   1. Based on the I_OFF, you can choose the value of C_HOLD based on what t_TEST and T_OUT you are comfortable with.
   2. Table 1 in the Analog Design Journal lists example values for these, I am copying the table below for your reference.
   3. 
3. Yes, the purpose of SUB pin is solely for improving thermal dissipation.
   1. Connecting SUB pin to FGND alters device functionality, therefore, they shouldn't be connected.
   2. The DNI resistor between SUB and FGND was left there for internal testing.

You mentioned Case #2 works from 8.7V to 9.2V only. Does this mean it doesn't work for 24V?
The solution is primarily tested for 24V, therefore, I expect the solution to work for 24V. For other voltages, the component values need to be optimized.

If you are facing issues at 24V, then share the following,

1. List the changes you have done to EVM.
   1. Please also share a picture showing the test / connection setup.
2. Share waveforms for Case #2 the way it is presented in the TI articles, i.e., Test pulse, VINx, C_HOLD and VOUTx.

Regards,
Koteshwar Rao

Hello Koteshwar,

Thank you for your answers

I changed the capacitor C_HOLD from 10nF to 220pF and repeated the test. and I notice that when the input of VINx is below 10,4 V I don't get any pulse at the output of VOUTx anymore. So case #2 doesn't actually work for me anymore.

In the attachments I put the waveforms from the oscilloscope which I captured as well as the picture of the test setup and the corrections on the schematic i made as you wanted.

The test signal is generated from a function generator with 50 Ohm termination.
rise and fall time of the signal is set to 1us. signal frequency is 100Hz and pulse width is 100us.
Signal amplitude is 3.3V

The voltage supply of the iso1211EVM is also at 3.3V
the modifications made to the ISO1211EVM are:
pins 5 and 6 are lifted off the PCB and are in the air. while pin 6 is connected to the collector of the optocoupler transistor. The emitter is connected to the FGND. The current through the optocoupler led diode is limited by 430 ohms. A generic ACPL-217-50DE optocoupler is used.

The waveforms show
- the test signal in blue,
- the output signal in yellow
- and the input signal in red.

For C_HOLD, I don't understand how did you measure since it is on the same node with VINx. Please if you can explain this.

0201_001.pdf

Hi Gorazd,

Thank you for sharing all the requested information, this is very helpful and helps me understand the situation better.

Gorazd Grkman said:

For C_HOLD, I don't understand how did you measure since it is on the same node with VINx. Please if you can explain this.

There is RTHR resistor between C_HOLD and VINx, therefore, these two voltages can be slightly different although they are going to be proportional.

It looks like you are connecting 24V supply to VINx pins to represent HIGH input and to make it LOW, you are bringing down the supply voltage. This is not going to work as the Wire-Break Detection circuit is made to work with an actual switch with a non-zero I_OFF. Please see below a few screenshots that talk about the I_OFF and describe the operation.

As described above, you would have to use a switch between 24V and VINx, switch ON/OFF to create HIGH/LOW Digital Inputs and include a resistor RMEG to supply IOFF current. You can choose RMEG to be 100kΩ so that there is sufficient current to charge CHOLD. Alternatively, you can avoid using a switch and simply connect 100kΩ between 24V and VINx to recreate switch OPEN condition.

Once this is done, you should see the pulse show up at OUT pin for Case #2.

Please note the following,

1. A lower RMEG allows better charging of CHOLD, therefore, 100kΩ is preferred to start with.
2. Higher CHOLD allows for holding more charge, therefore, start with 10nF and increase if needed as you test.
3. Higher the pulse width of test signal, higher the charge stored in CHOLD. Therefore, start with 24ms of pulse width and then you can decrease later if this is too much. I see that you have used a pulse width of approximately 100µs, we recommend that you start with 24ms.

Please consider all the above suggestions into your solution and it should work fine. Let me know your observation once you complete the test, thanks.

Regards,
Koteshwar Rao

Thank you for your explanation, it now works as described.
Rmeg plays an important role here. Thank you for pointing this out to me.

Now there is a play between the capacitor value, the supply voltage VINx and the pulse width.
With wider pulses everything works OK. With small pulses I have a issue because I can't charge the capacitor enough to make pulse at the output.

The wide pulse width is not acceptable in my application, because my STO circuit respond to it.

I also have a question about the OSSD pulses, will they interfere with the diagnostics?

Thank you very much for your reply.

Hi Gorazd,

Thank you for the update and I am glad to know that you were able to get the product working.

I do understand the concern on requiring wide pulse. The only other way to make it work without making the pulse wider, is to increase the leakage current by reducing RMEG so that the CHOLD charges faster.

Gorazd Grkman said:

I also have a question about the OSSD pulses, will they interfere with the diagnostics?

Can you please let me know what are OSSD pulses?

Regards,
Koteshwar Rao