This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi Team,
Customer would like to check the width of the layout recommendation for SOIC and SSOP package.
Could you provide the suggestions for the width?
www.ti.com/.../iso7741.pdf ,page 29
Thanks,
SHH
Hi Anand,
Does customer must to keep the width of the space as same as the package size? Can customer keep the width of the space less than 100mil?
Does customer must to do groove under the chip?
Thanks,
SHH
Hi SHH,
In order to achieve full isolation specifications, the creepage and clearance equal to that of the device package needs to be maintained on the PCB. If this is not maintained, the isolation specifications of the device listed in the datasheet cannot be guaranteed.
To give some more clarity, this is because the air can undergo a dielectric breakdown at higher voltages, leading to the high voltage passing from Gnd1 to Gnd2. Approximately 8mm of clearance needs to be kept so that 8kV of surge events can be tolerated without air breakdown happening. If this spacing is reduced the voltage at which air will breakdown is also lowered.
Customer can do a groove under the chip to increase the creepage distance through the PCB. In most cases the material grade of the PCB is lower than the material grade of the device package. This implies that to achieve the same isolation rating, the creepage distance through PCB material needs to be higher than the creepage distance through the device package. Having a groove can help achieve this extra creepage distance.
Please refer to the following E2E post where I have explained in detail about the significance of creepage distance through PCB.
https://e2e.ti.com/support/isolation/digital_isolators/f/1013/t/621581
Let me know if there are any doubts.
Regards,
Anand Reghunathan