AM572x Interrupt mapping for DSP and GMAC?

Kevin Halloran

Other Parts Discussed in Thread: AM5728, SYSBIOS

I am using the AM572EVM (Beagleboard X15) and attempting to modify the nimu example project for the DSP (NIMU_BasicExample_evmAM572x_armExampleproject, pdk_am57xx_1_0_0). I was able to get it working for the M4 & A15 and have rebuilt the PDK transport nimu libraries for the c66x successfully. Once I get interrupts mapped correctly it should work as the NDK can communicate with the PHY and initiate a connection with no problem from the DSP.

Where I am having a problem is understanding the interrupt mapping. The DSP low level seems to allow interrupts 4 to 15 but the crossbar needs to be set accordingly for CSL_XBAR_GMAC_SW_IRQ_RX_PULSE and CSL_XBAR_GMAC_SW_IRQ_TX_PULSE.

On the M4 it was set as follows:

CSL_xbarIpuIrqConfigure(1,CSL_XBAR_INST_IPU1_IRQ_76, CSL_XBAR_GMAC_SW_IRQ_RX_PULSE);
CSL_xbarIpuIrqConfigure(1,CSL_XBAR_INST_IPU1_IRQ_77, CSL_XBAR_GMAC_SW_IRQ_TX_PULSE);

and

#define GMAC_SW_IRQ_RX_PULSE_INT_NUM (76)
#define GMAC_SW_IRQ_TX_PULSE_INT_NUM (77)
#define GMAC_SW_IRQ_RX_THRESH_PULSE_INT_NUM (78)
#define GMAC_SW_IRQ_MISC_PULSE_INT_NUM (79)

---------------------------

My guess is I want to map the RX_PULSE to the DSP interrupt 4 and TX_PULSE to interrupt 5 at the DSP given the code does a range check in Sys/Bios HWI of 4 to 15.

I tried:

CSL_xbarDspIrqConfigure(1,CSL_XBAR_INST_DSP1_IRQ_35, CSL_XBAR_GMAC_SW_IRQ_RX_PULSE);
CSL_xbarDspIrqConfigure(1,CSL_XBAR_INST_DSP1_IRQ_36, CSL_XBAR_GMAC_SW_IRQ_TX_PULSE);

and

#define GMAC_SW_IRQ_RX_PULSE_INT_NUM (35)
#define GMAC_SW_IRQ_TX_PULSE_INT_NUM (36)
#define GMAC_SW_IRQ_RX_THRESH_PULSE_INT_NUM (37)
#define GMAC_SW_IRQ_MISC_PULSE_INT_NUM (38)

But that gives an invalid interrupt number error. I also tried below which is the actual defined value of CSL_XBAR_INST_DSP1_IRQ_35 for RX_PULSE.

#define GMAC_SW_IRQ_RX_PULSE_INT_NUM (4)
#define GMAC_SW_IRQ_TX_PULSE_INT_NUM (5)
#define GMAC_SW_IRQ_RX_THRESH_PULSE_INT_NUM (6)
#define GMAC_SW_IRQ_MISC_PULSE_INT_NUM (7)

which does not generate an error but I think then the crossbar setting is wrong since no interrupts are processed? Could use some help understanding the mapping as the Technical Reference Manual if hard to understand. Would be a good topic for a wiki document having some examples for the different cores. Any information or even a quick lesson in the DSP mapping would be helpful. Also if I possibly need a special module loaded in the xdc cfg file to handle the mapping?

I posted a similar question last week on the Sitara Forum and have had no luck getting a response. If I can get the interrupt mapping verified I can probably debug it from there.

https://e2e.ti.com/support/arm/sitara_arm/f/791/t/484858

Thanks,

Kev

over 9 years ago

0 Steven Connell over 9 years ago

TI__Mastermind 45025 points

Hi Kevin,

Kevin Halloran said:

I posted a similar question last week on the Sitara Forum and have had no luck getting a response. If I can get the interrupt mapping verified I can probably debug it from there.

https://e2e.ti.com/support/arm/sitara_arm/f/791/t/484858

Which SDK are you using? Can you please list the exact name of the SDK? I reviewed your other thread as well, and I'm not sure why Biser moved it to the TIRTOS forum. Your questions seem to be about examples that are specific to an SDK (Sitara SDK?), and which were not developed by the TIRTOS team. Anyway, knowing which SDK you are working with will help us get the right people looking at this thread.

Kevin Halloran said:
Where I am having a problem is understanding the interrupt mapping. The DSP low level seems to allow interrupts 4 to 15 but the crossbar needs to be set accordingly for CSL_XBAR_GMAC_SW_IRQ_RX_PULSE and CSL_XBAR_GMAC_SW_IRQ_TX_PULSE.

Kevin Halloran said:
#define GMAC_SW_IRQ_RX_PULSE_INT_NUM (4)
#define GMAC_SW_IRQ_TX_PULSE_INT_NUM (5)
#define GMAC_SW_IRQ_RX_THRESH_PULSE_INT_NUM (6)
#define GMAC_SW_IRQ_MISC_PULSE_INT_NUM (7)

I'm not at all familiar with the crossbar, nor the GMAC. Are these peripherals on the device?

Kevin Halloran said:
Once I get interrupts mapped correctly it should work as the NDK can communicate with the PHY and initiate a connection with no problem from the DSP

It sounds like you have the networking side of things working?

Kevin Halloran said:
My guess is I want to map the RX_PULSE to the DSP interrupt 4 and TX_PULSE to interrupt 5 at the DSP given the code does a range check in Sys/Bios HWI of 4 to 15.

If you need help configuring the SYS/BIOS Hwi module, then we can help you on this forum. However, it seems like there is some interrupt configuration wrapper API that you are using, that's maybe part of the SDK. If this is the case, then we need the SDK owners to help on this.

Steve

0 Kevin Halloran over 9 years ago in reply to Steven Connell

Expert 1345 points

Steve, thanks for getting back to me. I believe I have the hard part working, getting the NDK and PHY rebuilt and working for the c66x. Once the interrupts start working all should work but the mapping on the AM5728 is very obscure internal to the chip and the documentation is sparse. I have a feeling I missed something at the mapping layer since I was able to debug the Sysbios/HWI and see the limitation to interrupts 4 to 15.

The SDK is the "Processor SDK RTOS for AM57xx", Release 02.00.00. I just noticed there is a newer version that I will update to as well that was put up recently( R02.00.01.07). I noticed they included the nimu support for the c66x in that build which was really just a make file modification. Example code still only supports the A15 core, M4 and C66 examples for Ethernet are not there. M4 I did myself, C66x is the one I need help with in regards to mapping of interrupts.

0 Steven Connell over 9 years ago in reply to Kevin Halloran

TI__Mastermind 45025 points

Kevin,

Maybe you need to use the Event Combiner? The Event Combiner allows the mapping of many events into a single Hwi.

You can see example code for the Event Combiner in the SYS/BIOS documentation. For example, this doc is here on my PC:

C:/ti/BIOS/bios_6_42_03_35/docs/cdoc/index.html

Steve

0 Kevin Halloran over 9 years ago in reply to Steven Connell

Expert 1345 points

Steve,

Thanks for your post, it gave me a hint. It is frustrating that TI does not have fundamental examples for their new chips (AM5728) on something like mapping interrupts for the DSP. The Technical Manual is far too obscure. I finally figured it out and you are on the right track. This could use a good wiki application tip. After days of banging my head trying to get the NDK to work on the DSP side of the AM5728 I finally found the PDK does not have all the support needed at the nimu layer and needed modification for proper interrupt mapping. Right now it is a hack but I can ping the NDK running on the DSP of the AM5728, just have to figure out how to clean it up a bit so I can post it. Thanks to a post a year ago I was able to figure it out how to map DSP interrupts:

e2e.ti.com/.../408040

A generic routine would be something like this:

#include <ti/sysbios/family/c64p/EventCombiner.h>
#include <ti/sysbios/family/shared/vayu/IntXbar.h>

/*
* Example 1:
* crossbar_input = CSL_XBAR_GMAC_SW_IRQ_RX_PULSE
* dspEvent = CSL_XBAR_INST_DSP1_IRQ_76
* dspInterrupt = 4 (4 to 15 are valid but verify what is being used)
* fxn = Cpsw_HwIntRx(), PDK Rx function in cpsw_ethdriver.c
*
* Example 2:
* crossbar_input = CSL_XBAR_GMAC_SW_IRQ_TX_PULSE
* dspEvent = CSL_XBAR_INST_DSP1_IRQ_77
* dspInterrupt = 5 (4 to 15 are valid but verify what is being used)
* fxn = Cpsw_HwIntTx(), PDK Tx function in cpsw_ethdriver.c
*
*/
Hwi_Handle map_AM5728_DSP_interrupts(int dspInterrupt, int dspEvent, int crossbar_input, ti_sysbios_family_c64p_EventCombiner_FuncPtr fxn)
{
Hwi_Params params;
Error_Block eb;

IntXbar_connectIRQ(dspEvent, crossbar_input); // Maps crossbar input to DSP event

/* Plug an ISR for DSP event */
EventCombiner_dispatchPlug(dspEvent, fxn, dspEvent, TRUE);

Hwi_Params_init(&params);

params.eventId = dspEvent / 32;
params.arg = params.eventId;
params.enableInt = TRUE;

Hwi_Handle handle = Hwi_create(dspInterrupt, &EventCombiner_dispatch, &params, &eb);
return handle;
}

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AM572x Interrupt mapping for DSP and GMAC?