I am using the AM572EVM (Beagleboard X15) and attempting to modify the nimu example project for the DSP (NIMU_BasicExample_evmAM572x_armExampleproject, pdk_am57xx_1_0_0). I was able to get it working for the M4 & A15 and have rebuilt the PDK transport nimu libraries for the c66x successfully. Once I get interrupts mapped correctly it should work as the NDK can communicate with the PHY and initiate a connection with no problem from the DSP.
Where I am having a problem is understanding the interrupt mapping. The DSP low level seems to allow interrupts 4 to 15 but the crossbar needs to be set accordingly for CSL_XBAR_GMAC_SW_IRQ_RX_PULSE and CSL_XBAR_GMAC_SW_IRQ_TX_PULSE.
On the M4 it was set as follows:
CSL_xbarIpuIrqConfigure(1,CSL_XBAR_INST_IPU1_IRQ_76, CSL_XBAR_GMAC_SW_IRQ_RX_PULSE);
CSL_xbarIpuIrqConfigure(1,CSL_XBAR_INST_IPU1_IRQ_77, CSL_XBAR_GMAC_SW_IRQ_TX_PULSE);
and
#define GMAC_SW_IRQ_RX_PULSE_INT_NUM (76)
#define GMAC_SW_IRQ_TX_PULSE_INT_NUM (77)
#define GMAC_SW_IRQ_RX_THRESH_PULSE_INT_NUM (78)
#define GMAC_SW_IRQ_MISC_PULSE_INT_NUM (79)
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My guess is I want to map the RX_PULSE to the DSP interrupt 4 and TX_PULSE to interrupt 5 at the DSP given the code does a range check in Sys/Bios HWI of 4 to 15.
I tried:
CSL_xbarDspIrqConfigure(1,CSL_XBAR_INST_DSP1_IRQ_35, CSL_XBAR_GMAC_SW_IRQ_RX_PULSE);
CSL_xbarDspIrqConfigure(1,CSL_XBAR_INST_DSP1_IRQ_36, CSL_XBAR_GMAC_SW_IRQ_TX_PULSE);
and
#define GMAC_SW_IRQ_RX_PULSE_INT_NUM (35)
#define GMAC_SW_IRQ_TX_PULSE_INT_NUM (36)
#define GMAC_SW_IRQ_RX_THRESH_PULSE_INT_NUM (37)
#define GMAC_SW_IRQ_MISC_PULSE_INT_NUM (38)
But that gives an invalid interrupt number error. I also tried below which is the actual defined value of CSL_XBAR_INST_DSP1_IRQ_35 for RX_PULSE.
#define GMAC_SW_IRQ_RX_PULSE_INT_NUM (4)
#define GMAC_SW_IRQ_TX_PULSE_INT_NUM (5)
#define GMAC_SW_IRQ_RX_THRESH_PULSE_INT_NUM (6)
#define GMAC_SW_IRQ_MISC_PULSE_INT_NUM (7)
which does not generate an error but I think then the crossbar setting is wrong since no interrupts are processed? Could use some help understanding the mapping as the Technical Reference Manual if hard to understand. Would be a good topic for a wiki document having some examples for the different cores. Any information or even a quick lesson in the DSP mapping would be helpful. Also if I possibly need a special module loaded in the xdc cfg file to handle the mapping?
I posted a similar question last week on the Sitara Forum and have had no luck getting a response. If I can get the interrupt mapping verified I can probably debug it from there.
https://e2e.ti.com/support/arm/sitara_arm/f/791/t/484858
Thanks,
Kev