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TPS3808-EP: Timeout Delay tolerance/variation

Chris Kayley
Prodigy 10 points
Part Number: TPS3808-EP

We are looking to use the TPS3808G33 as a reset supervisor to a Ti DSC. We are looking to implement a 20ms delay and so leaving the Ct pin open circuit.

We require a tight tolerance (+- 10%) of this time over the temperature range -55 to +110. In part 6.6 it states a minimum td time of 12ms and a maximum of 29ms, are these values given over the operating temperature? If so they dont seem to align to the data given in figure 4 which shows a variation of +6% to -1% in the reset time.

Can it be clarified about the tolerance of the timeout time for the IC?

Thanks

Chris

  • 0
    TI__Mastermind 20045 points
    Hello Chris,

    Figure 4 shows typical percent changes over temperature. Section 6.6 (12ms to 29ms) encompasses temperature and other variations (due to process, Vdd, etc.).

    Note that figure 4 is not a guarantee of maximum variation. Section 6.6 is intended to represent the worst case max and min over the given conditions. However, like I said, it encompasses other variation not just due to temperature. I hope that helped clarify.

    Thanks,
    Kyle