Hello,
I am currently planning on using this device in my design, as I have a very high speed parallel data bus (330 Mbps so 165 MHz) that has 10 bits of data, a clock and a sync signal which all need to be transmitted with 0.6 ns or less of skew between signals. This requirement comes from me needing to transmit these signals as LVDS to another board with LVDS receivers which will use this data bus. The LVDS driver part I am using is the TI DSLVDS1047PWR, which has a part to part propagation delay variance/range of 1.2 ns (max is 1.7 ns, min is 0.5 ns). Since there will also be a set of LVDS receivers on the other end, and each of these separate components could have different propagation delays from process variation, I need to ensure that the worst case range in propagation delay falls within a half-clock period (since this bus is transmitting data at DDR) which is ~3 ns.
Is there any guarantee that the SN74AVC20T245 will have less than a certain maximum skew between two output channels in different buses on the same device? I saw that someone asked a similar question in this forum: "SN74AVC20T245: Propagation Delay of signal groups / individual signals", but I need to clarify whether or not I can assume that the skew between signals that are on the same IC but different ports/buses (10-bit A group vs 10-bit B group) are also within this constraint, since my 12-bit bus requires that I use channels on both ports A and B of this device. For context all of the signals I am level shifting will have the same load as they are all on the same parallel bus.
This tight requirement is a result of needing to convert 1.8V single-ended signals to LVDS to transmit them, if there are any other TI parts that handle this better I would appreciate being pointed in that direction.
