SN74AXC8T245-Q1: VOH and VOL when VCCA=1.8 and VCCB=2.5

Z78M12

Prodigy 85 points

Part Number: SN74AXC8T245-Q1

Hi,

What will be VOH and VOL when VCCA=1.8V and VCCB=2.5V

over 3 years ago

0 Albert Xu1 over 3 years ago

TI__Mastermind 38535 points

Hi,

These two FAQs may be able to help:

[FAQ] How do I determine the output voltage (VOH, VOL) or output current (IOH, IOL) of a CMOS logic device?

[FAQ] What method is best used for estimating specification values between those given in the datasheet?

Datasheet values are set parameters the device is tested at. Anything not on the datasheet, we can't guarantee any values.

0 Z78M12 over 3 years ago in reply to Albert Xu1

Prodigy 85 points

Thanks.

So in both links, it's only VCCB that involved in the linear interpolation?
If so, why VCCA mention in the datasheet in regarding the VOH?

Or in other worlds:
VOH when VCCA=1.8 and VCCB=2.5 its the same as
VOH when VCCA=VCCB=2.5?

Another question is regarding the Max data rate:
The datasheet declare "Up to 380 Mbps support when translating from 1.8 V to 3.3 V"
but tpd in this case is 4/5 ns max (200 Mbps- 250Mbps).
Can you explain?
If I'm using VCCA=1.8 VCCB=2.5 (tp=5nS max), so I can't use if for CLK of 100MHz as it on the edge?

+1 Dylan Hubbard over 3 years ago in reply to Z78M12

TI__Mastermind 46045 points

Hi Ziv,

The VOL/VOH specifications only depend on the output supply which can either be the A or B port. This is why both supplies are listed. The supply for the input port does not impact the output port in this regard.

The Tpd doesn't represent the maximum data rate, rather the delay time for the signal propagates through the device. The data rate will be limited by the capabilities of the output driver and the capacitive load. This device should be able to handle 100MHz with those supplies.

What interface will this device be used for?

0 Z78M12 over 3 years ago in reply to Dylan Hubbard

Prodigy 85 points

It's a dedicated parallel 8 bits interface (unidirectional) we send over Ser(913)/Des(914).
We are using the device between Deserilizer (DS90UB914) and our FPGA.
Deserilizer VDDIO is 1.8V while the FPGA is LVCMOS 2V5.

Signal 1: is PCLK, 100 MHz.
Signal 2: 100nS pulse width, 4-5 uS period.
Signal 3: changing, 120nS to 1uS pulse width, 4-5 uS period.

The other signals are slower.

+1 Dylan Hubbard over 3 years ago in reply to Z78M12

TI__Mastermind 46045 points

Hi Ziv,

Thanks for the info, the AXC family is our fasted low voltage translation family and should work here.

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SN74AXC8T245-Q1: VOH and VOL when VCCA=1.8 and VCCB=2.5