Bus hold circuit review

Chitharanjan M1

Hi,

In my design, I have provided a bus-hold circuit for the GPIO PIO0_18(EN2) & PIO0_22(EN1).

The purpose of bus-hold circuit is to hold the previous state of GPIO level during the tristate. I have attached the schematic below for review.

Please review and let me know your feedback.

Regards,

Chitharanjan

over 3 years ago

0 Clemens Ladisch over 3 years ago

Guru 316440 points

The bus-hold circuit itself is OK.

But bus hold cannot be used with a pull-down resistor; when the bus holder pulls high, you have a voltage divider. Do you want EN_1 to be low, or the last state?

0 Chitharanjan M1 over 3 years ago in reply to Clemens Ladisch

Intellectual 360 points

Hi Clemens,

Thanks for the reply......

I want EN_1 to be the last state.

Pull up and pull down are optional when the bus-hold circuit presents pulldown/up will be DNP.

Regards,

Chitharanjan

0 Emrys Maier over 3 years ago in reply to Chitharanjan M1

TI__Guru* 97046 points

Hi Chitharanjan,

Looks fine to me. Just note that R253 is not marked as DNP, which is probably why Clemens was asking. If that is not populated, then there is no issue.

Logic

Logic forum

Bus hold circuit review