• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 2 answers
  • Subscribers 20 subscribers
  • Views 374 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN74LVC1G74: Implication of slow falling clock edge

Boris Savov
Prodigy 10 points
Part Number: SN74LVC1G74
Other Parts Discussed in Thread: SN74LVC1G17, SN74HCS74

The application is Power On/Off button control.
There is R-C delaying circuit on the CLK input which makes the rising and falling edges of the clock slower than the max recommended in the datasheet (at 3.3V) 10ns.
Although the flip-flop works fine at the slow rising CLK edge, it changes its state also when the CLK goes down at almost the same slow rate of 500ns/V.
Is this behaviour expected?
If a comparator is placed on front of the CLK to rectify the slow fall time edge, will it fix the unexpected flip-flop change state?

  • 0
    TI__Genius 17960 points

    Hi Boris,

    Is the RC circuit necessary on the CLK input? 

    Yes the behavior will be expected since you're violating the input transition rate requirements. There is some noise on the falling edge of your clock signal that is causing the device to trigger. Please see this FAQ How does a slow or floating input affect a CMOS device? for further details. 

    You could place a comparator to rectify the slow fall edge time if the comparator has a fast enough switching time to meet the input transition rate requirements. 

    Regards,

    Sebastian 

  • 0
    Guru 316470 points

    A simple Schmitt-trigger buffer (e.g., SN74LVC1G17) is enough to get a proper signal.

    Alternatively, use a flip-flop with Schmitt-trigger inputs, e.g., SN74HCS74.

  • 0 in reply to Clemens Ladisch
    Prodigy 10 points

    Thanks for the suggestions!
    It is fixed by decreasing the CLK fall time.
    BTW, it turns out the installed chip is not TI, but Nexperia and its datasheet claims that all inputs are schmitt trigger inputs.
    Though, both TI and Nexperia note the same max value for edge rise/fall time - 10 ns/V.
    The fix still includes higher than 10 ns/V fall time, but it works reliably.
    Cheers,
    Boris

  • 0 in reply to Boris Savov
    Guru 316470 points

    "Schmitt-trigger action" is not the same as real Schmitt-trigger inputs. All LVC inputs (from any manufacturer) have a little bit of hysteresis, but this is only to compensate for the inductance of the pins and the bond wires at high frequencies.