Other Parts Discussed in Thread: SN74LVC2G66
Hi,
I am using the TXS0102 device to interface the MDIO signals between my Processor and the TI DP83867 ethernet phy device.
I have a query on the Rise time/ Fall time specifications in the TXS0102 datasheet "SCES640I –JANUARY 2007–REVISED OCTOBER 2018"
In my case VCCA = VCCB =3.3V.
I am referring section 6.11 Switching Characteristics: VCCA = 3.3 V ± 0.3 V.
Here I am checking the column VCCB = 3.3V+/- 0.2V.
My query is with respect to "tfB Input fall time", B port fall time which is specified as maximum 7.4ns for Push pull driving .
In my board, I measure the fall time for the B input as (from 10% to 90% of steady stage Vhigh) as ~12ns.
- I would like to understand what is the impact of having 12ns fall time at the TXS0102 B input as against the spec of max 7.4ns?
- Is meeting 7.4ns fall time at B input a requirement and not meeting it cause unexpected behavior of TXS0102?
- Or it 7.4ns Fall time spec with 15pF parallel with 1Mohm load. If I have have higher capacitance at output, the Fall time may increase but will not cause unexpected behavior of the TXS0102?
Thanks
Louis