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Hi,
I am using the TXS0102 device to interface the MDIO signals between my Processor and the TI DP83867 ethernet phy device.
I have a query on the Rise time/ Fall time specifications in the TXS0102 datasheet "SCES640I –JANUARY 2007–REVISED OCTOBER 2018"
In my case VCCA = VCCB =3.3V.
I am referring section 6.11 Switching Characteristics: VCCA = 3.3 V ± 0.3 V.
Here I am checking the column VCCB = 3.3V+/- 0.2V.
My query is with respect to "tfB Input fall time", B port fall time which is specified as maximum 7.4ns for Push pull driving .
In my board, I measure the fall time for the B input as (from 10% to 90% of steady stage Vhigh) as ~12ns.
Thanks
Louis
Requirements can be found in sections 6.3 and 6.8. I do not know what the meaning of those entries in section 6.11 is.
Anyway, the TXS is a passive switch and makes sense only when you actually want to do level shifting. With VCCA = VCCB, you can replace it with two wires.
Hi Louis,
In addition to Clemens' feedback, please note that there is no concern if your application do not have specific timing requirements; as long as the input transition rate is within the datasheet's recommendation.
It would also be case by case and dependent on your system per it's total capacitance as well. Please help see [FAQ] What is the output transition rate for a logic device? for further clarification on the loading, thanks.
Best Regards,
Michael.
Thanks for the response Clemens.
1. We are using the TXS0102 not as a level translator but to enable/ disable MDIO to an external board based on CPU control. We use the OE pin to tristate the IO to external board by default and enable under software control.
2. Ok, Thanks. So Switching characteristics in section 6.11 is not a requirement.
Ok, Thanks. So Switching characteristics in section 6.11 is not a requirement.
We need to ensure that input transition rate spec of 10ns/V max is not exceeded.
To disconnect the bus, a plain switch like the SN74LVC2G66 would be simpler and cheaper.