SN74AUP1G32: Output(Y) abnormal Waveform Issue

Dear Sir:

IC (SN74AUP1G32)Input transition rise and fall rate Spec. max 200nsec/V

1. Regarding the Rise/Fall Time definition.

Does  Rise/Fall Time define 10~90% (the 10% and 90% reference levels)?  Is it correct?

2. The input of SN74AUP1G3 level is 3V

The input of SN74AUP1G3 level 90% : 3V*0.9 = 2.7V

The input of SN74AUP1G3 level 10% : 3V*0.1 = 0.3V

Δv = level 90% - level 10% = 2.7-0.3 = 2.4V

Input transition rise and fall rate max.(200ns/V)

The rise/ Fall time max = 200ns *2.4V = 480ns(max). Is the calculation correct?

Please check to reply us asap.

Thanks a lot.

Best Regards,

Vincent

The rate (ns/V) describes the slope of the edge. The edge must not be slower than that, at any point of the edge. The rise/fall time alone cannot describe this.

You have not shown the schematic. But a R-C debouncing circuit requires a device with Schmitt-trigger input.

Dear Sir:

Do you mean the above calculation is not correct?

Could you provie us with the more detailed?

When we measure the rise/ fall time value . How to calculate the Input transition rise and fall rate (ns/V)?

Please check to reply us asap.

Thanks a lot.

Best regards,

Vincent

Dear Sir:

1. Due to the output of SN74AUP1G32 abnormal waveform.

It can't use the abnormal waveform rise/fall time to calculate the Input transition rise and fall rate (ns/V). it isn't suitable.

Is it correct?

2. On the other hand. If the output of SN74AUP1G32 normal waveform.

Whether it can calculate the Input transition rise and fall rate (ns/V)?

Is the following calculation correct?

For Example:

(1) Rise Time: 13.74us

The input of SN74AUP1G3 level is 3V

The input of SN74AUP1G3 level 90% : 3V*0.9 = 2.7V

The input of SN74AUP1G3 level 10% : 3V*0.1 = 0.3V

Δv = level 90% - level 10% = 2.7-0.3 = 2.4V

Input transition rise rate is 13.74us/2.4V = 5.725us/V  > 200ns/V (Max).

Input transition rise rate can't meet the 200ns/V (Max).

(2) Fall Time: 16.16us

The input of SN74AUP1G3 level is 3V

The input of SN74AUP1G3 level 90% : 3V*0.9 = 2.7V

The input of SN74AUP1G3 level 10% : 3V*0.1 = 0.3V

Δv = level 90% - level 10% = 2.7-0.3 = 2.4V

Input transition fall rate is 16.16us/2.4V = 6.733us/V  > 200ns/V (Max).

Input transition fall rate can't meet the 200ns/V (Max).

Is the calculation correct?

Please check to reply us asap.

Thanks a lot.

Best regards,

Vincent

Rise Time: 13.74us

Fall Time: 16.16us

The rise/fall time does not matter. The datasheet does not even mention the rise/fall time.

When the input is switching, the input voltage must have a fast enough rise/fall rate to prevent oscillations; see the FAQ I linked. The switching happens somewhere between V_IL and V_IH. I've marked these limits (0.9 V and 2 V) in red below.

In your circuit, the slowest part of the edge is where it crosses V_IH. I've drawn the tangent at that point in green. The slope of the green line is more than 5000 ns/V, which is much larger than the allowed 200 ns/V.

Dear Sir:

Regarding Insert a Schmitt-trigger buffer (e.g., SN74AUP1G17) into the slow signal line.

The output of Schmitt-trigger buffer connects to the input of SN74AUP1G32(OR Gate).

1. Whether it considers to add the series damping resistor and capacitor(Parallel) RC circuit (e.g., overshoot/undershoot improve ) between the output of Schmitt-trigger buffer and the input of SN74AUP1G32(OR Gate)?  

If need to consider. Please provide us with the recommend series damping resistor and capacitor(Parallel).

2. Between the output of Schmitt-trigger buffer and the input of SN74AUP1G32(OR Gate)'s the pull down Resistor.

 The output of Schmitt-trigger buffer (e.g., SN74AUP1G17) doesn't define the IOL(leakage).

The input current (Ii) of SN74AUP1G32(OR Gate) is 0.5uA(max)

The input VIL of SN74AUP1G32(OR Gate) is 0.9V

Calculate the maximum value for the pull-down resistor: VIL/ Ii = 0.9V/ 0.5uA = 1.8M ohm.

Is the calculation correct?

Please check to reply it asap.

Thanks a lot.

 Best Regards.

Vincent

Dear Sir:

2. But the output of the Schmitt-trigger buffer is always active; so if both the buffer and the OR gate are powered by the same supply, you do not need the pull-down.

-->  the Schmitt-trigger buffer and the OR gate are powered by the same supply ( VCC = 3V )

If no pull -down resistor. the output of the Schmitt-trigger buffer connects the input of OR gate.

Is the connection signal wire status is floating? is floating  OK?

Please check to reply us asap.

Thanks a lot.

Best Regards,

Vincent

The SN74AUPxG17 does not have any function to disable its output. The output is always active, i.e., it is always driven either high or low.

Dear Sir:

1.The output of SN74AUPxG17 Schmitt-trigger buffer can connect to the input of OR gate directly without pull-down Resistor. Is it correct?

2.The output of SN74AUPxG17 Schmitt-trigger buffer connects to the OE\ pin of SN74AUP1G125(3-State ). It Is still no need the pull-down resistor. Is it correct?

3. The output of SN74AUPxG17 Schmitt-trigger buffer can connect to the input(PIN2) of SN74AUP1G125(3-State) directly without pull-down Resistor. Is it correct?

4.  SN74AUP1G125(3-State with OE/ pin) can disable the output function.  

So the output of SN74AUP1G125 needs the external pull-down resistor. Is it correct?

Please check to reply us asap.

Thanks a lot.

Best Regards,

Vincent

All four are correct.

Dear Sir:

An RC circuit should not be necessary because AUP outputs do not generate sharp edges

-->

1.AUP means the AUP family IC. Is it correct?

2. The 3 Items IC SN74AUPxG17,SN74AUP1G125 and SN74AUP1G32 all belong to the AUP family IC.  Is it correct?

SN74AUPxG17 (SCHMITT-TRIGGER BUFFER)

SN74AUP1G125(Single Bus Buffer Gate With 3-State Output)

SN74AUP1G32(Single 2-Input Positive-OR Gate)

3.SN74AUPxG17,SN74AUP1G125 and SN74AUP1G32 outputs do not generate sharp edges. Is it correct?

Please check to reply us asap.

Thanks a lot.

B.R

Vincent  

Correct.

Dear Sir:

Are all the above 3 items correct?

Thanks a lot.

Best Regards.

Vincent

Yes.

Dear Sir:

SN74AUP1G32(Single 2-Input Positive-OR Gate)

The current of input(Ii) is 0.5uA.

The 2-input(A & B)  total curent : 2 * 0.5uA = 1uA. Is it correct.

Please check to reply it asap.

Thanks a lot.

Best Regards

Vincent

This is correct; CMOS inputs have an extremely high impedance. (And that 0.5 µA is the worst case at the most extreme temperature; typical input current is orders of magnitude smaller.)

Dear Sir:

1. Calculation SN74AUP1G32(OR Gate) Pull-Down RES Range:

(1) A: SoC ACC_OFF_837 Output max current : 4mA.

   ACC_OFF_837 Voltage Level : 3.3V.

   B : Consider the Schmitt Trigger Buffer(SN74AUP1G17) : Inrush current 3.3mA

   C: OR Gate(SN74AUP1G32) II A inputs (max ) = 0.5uA

   Pull-Down RES (min): 3.3V/(4mA-3.3mA-0.5uA)= 3.3V/0.6995mA=4.717Kohm.

(2)The input current (Ii) of SN74AUP1G32(OR Gate) is 0.5uA(max)

   The input current (Ii2) of SN74AUP1G17 (Schmitt Trigger Buffer) is 0.5uA(max)

   The input VIL of SN74AUP1G32(OR Gate) is 0.9V

   Calculate the maximum value for the pull-down resistor: VIL/ (Ii+Ii2) = 0.9V/ (0.5uA+0.5uA) = 900Kohm.(Max)

   Pull-Down RES Range : 4.717Kohm ~ 900Kohm.

      2. Due to consider that ACC_OFF_837 have had the Pull-Down RES (R248 100Kohm) already.

Use the Pull-Down RES (R248 100Kohm).

Whether Pull-Down(100Kohm) is OK? Does Pull-Down(100Kohm) have problem?

     3. According to Pull-Down RES Range : 4.717Kohm ~ 900Kohm.

Select the mid value around 450Kohm as pull-down resistor for

Is Pull-Down(450Kohm) better than Pull-Down(100Kohm)?

Please check to reply it asap.

Thanks a lot.

Best regards,

Vincent

Dear Sir:

Regarding the SN74AUP1G32 (OR Gate).

Boot Sequence.

1st: The input(B) of SN74AUP1G32(OR Gate) changes from Low to High.

The input(B) signal rise time doesn't exceed the Δt/Δv Input transition rate max.(200ns/V).

The Output(Y) of SN74AUP1G32(OR Gate) changes from Low to high normally.

the output(Y)rise time is shorter than the propagation delay.

The Output(Y) rises done. and Keep High already.

2nd: The input(A) of SN74AUP1G32(OR Gate) changes from Low to High also

The input(A) signal rise time doesn't exceed the Δt/Δv Input transition rate max.(200ns/V).

When Both Input(A & B) pin SN74AUP1G32(OR Gate) keep high and the Output(Y) of SN74AUP1G32(OR Gate) keep high.

3rd:

At this time.

The input(B) of SN74AUP1G32(OR Gate) changes from High to Low.

The input(B)fall time exceed the Δt/Δv Input transition rate max.(200ns/V).

It will not cause the output Output(Y) of SN74AUP1G32(OR Gate) function abnormal work.

The output(Y) of SN74AUP1G32(OR Gate) Still Keep High and work function normally.

Is it correct?

Please check to reply it asap.

Thanks a lot.

Best Regards

Vincent

Dear Sir:

 An RC circuit should not be necessary because AUP outputs do not generate sharp edges

--->  Because AUP outputs do not generate sharp edges, the output of SN74AUP3G17(Schmitt-trigger buffer) can connect to the input of SN74AUP1G32(OR Gate) directly.

Is it correct?

Please check to reply us asap.

Thanks

B.R

Vincent

Yes.

Dear Sir:

An RC circuit should not be necessary because AUP outputs do not generate sharp edges

-->

1. We measure the actual waveform the output (Buffer Pin4) of SN74AUP1G25 (BUFFER)

The output (Buffer Pin4) waveform is not sharp edge overshoot.

The output (Buffer Pin4) waveform is low overshoot. Low Noise – Overshoot and Undershoot <10% of VCC [ VCC =3V , 10% of VCC = 0.3 ]

Is it correct?

2. SN74AUP1G32(OR Gate)

Absolute Maximum Ratings : The input voltage(VI) (max) of SN74AUP1G32 (OR Gate) is 4.6V

The output (Buffer Pin4) waveform max voltage level of SN74AUP1G25 (BUFFER) is 3.34 V < 4.6V.

It doesn't cause the SN74AUP1G32(OR Gate) damage.

Is it correct?

Please check to reply us the above items asap.

Thanks a lot.

Best regards,

Vincent

Correct.

Dear Sir:

Are the above 2 items all correct?

Please check to reply us asap.

Thanks a lot.

Best regards,

Vincent

Yes.