SN74AUP1G08: how low the rising slope will cause oscillation in logic gate?

Ann_Lien

Part Number: SN74AUP1G08
Other Parts Discussed in Thread: SN74HCS08, SN74AUP1G97, SN74LVC1G97

Hello expert,

In [FAQ] How does a slow or floating input affect a CMOS device?, it mentions there is oscillation when the input lingers near the threshold value (typically 1/2*Vcc). May we know how low the rising edge slope will cause oscillation in logic gate? Thanks a lot!

https://e2e.ti.com/support/logic-group/logic/f/logic-forum/737694/faq-how-does-a-slow-or-floating-input-affect-a-cmos-device

Best regards,

Ann Lien

over 2 years ago

0 Clemens Ladisch over 2 years ago

Guru 284840 points

The specified Δt/Δv limit is 200 ns/V.

0 Wenmin Hua over 2 years ago in reply to Clemens Ladisch

TI__Prodigy 450 points

Hi Ann and Clemens,

The same question is from my side. Is there any AND-gate device support 'Input transition rise or fall rate' up to 15ms/V?

Thanks a lot.

BR.

Wenmin Hua

0 Clemens Ladisch over 2 years ago in reply to Wenmin Hua

Guru 284840 points

You need Schmitt-trigger inputs to support slow edges.

AND gates with Schmitt-trigger inputs exist only with four channels (SN74HCS08) or as a configurable gate (SN74LVC1G97, SN74AUP1G97).

0 Wenmin Hua over 2 years ago in reply to Clemens Ladisch

TI__Prodigy 450 points

Hi Clemens,

Thanks for the feedbacks. But I don't find the same statement about slow rate of SN74LVC1G97 or SN74AUP1G97 as SN74HCS08 like below, unlimited input transition rise and fall rate.

Do SN74LVC1G97 and SN74AUP1G97 have the same feature?

Thanks a lot.

Wenmin Hua

0 Clemens Ladisch over 2 years ago in reply to Wenmin Hua

Guru 284840 points

The absence of such a specification means that there is no limit.

And the '97 datasheets explicitly say that they have "Schmitt-trigger inputs, which allows for slow input transition and better switching-noise immunity at the input."

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SN74AUP1G08: how low the rising slope will cause oscillation in logic gate?